fp.isa (12849:7f43ad13ebf0) fp.isa (13612:12ae022f3a30)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 Riscv Developers
4// Copyright (c) 2016-2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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86 }
87 default:
88 fault = std::make_shared<IllegalFrmFault>(ROUND_MODE,
89 machInst);
90 break;
91 }
92
93 if (fault == NoFault) {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 Riscv Developers
4// Copyright (c) 2016-2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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86 }
87 default:
88 fault = std::make_shared<IllegalFrmFault>(ROUND_MODE,
89 machInst);
90 break;
91 }
92
93 if (fault == NoFault) {
94 MiscReg FFLAGS = xc->readMiscReg(MISCREG_FFLAGS);
94 RegVal FFLAGS = xc->readMiscReg(MISCREG_FFLAGS);
95 std::feclearexcept(FE_ALL_EXCEPT);
96 %(code)s;
97 if (std::fetestexcept(FE_INEXACT)) {
98 FFLAGS |= FloatInexact;
99 }
100 if (std::fetestexcept(FE_UNDERFLOW)) {
101 FFLAGS |= FloatUnderflow;
102 }

--- 27 unchanged lines hidden --- 		95 std::feclearexcept(FE_ALL_EXCEPT);
96 %(code)s;
97 if (std::fetestexcept(FE_INEXACT)) {
98 FFLAGS |= FloatInexact;
99 }
100 if (std::fetestexcept(FE_UNDERFLOW)) {
101 FFLAGS |= FloatUnderflow;
102 }

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