compressed.isa (12369:6811cd264242) | compressed.isa (12428:ddc6b7179c81) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2015 RISC-V Foundation 4// Copyright (c) 2017 The University of Virginia 5// All rights reserved. 6// 7// Redistribution and use in source and binary forms, with or without 8// modification, are permitted provided that the following conditions are --- 22 unchanged lines hidden (view full) --- 31def format CROp(code, *opt_flags) {{ 32 iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags) 33 header_output = BasicDeclare.subst(iop) 34 decoder_output = BasicConstructor.subst(iop) 35 decode_block = BasicDecode.subst(iop) 36 exec_output = BasicExecute.subst(iop) 37}}; 38 | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2015 RISC-V Foundation 4// Copyright (c) 2017 The University of Virginia 5// All rights reserved. 6// 7// Redistribution and use in source and binary forms, with or without 8// modification, are permitted provided that the following conditions are --- 22 unchanged lines hidden (view full) --- 31def format CROp(code, *opt_flags) {{ 32 iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags) 33 header_output = BasicDeclare.subst(iop) 34 decoder_output = BasicConstructor.subst(iop) 35 decode_block = BasicDecode.subst(iop) 36 exec_output = BasicExecute.subst(iop) 37}}; 38 |
39def format CIOp(imm_code, code, *opt_flags) {{ | 39def format CIOp(imm_code, code, imm_type='int64_t', *opt_flags) {{ |
40 regs = ['_destRegIdx[0]','_srcRegIdx[0]'] | 40 regs = ['_destRegIdx[0]','_srcRegIdx[0]'] |
41 iop = InstObjParams(name, Name, 'ImmOp<int64_t>', | 41 iop = InstObjParams(name, Name, 'ImmOp<%s>' % imm_type, |
42 {'code': code, 'imm_code': imm_code, 43 'regs': ','.join(regs)}, opt_flags) 44 header_output = ImmDeclare.subst(iop) 45 decoder_output = ImmConstructor.subst(iop) 46 decode_block = BasicDecode.subst(iop) 47 exec_output = ImmExecute.subst(iop) 48}}; 49 | 42 {'code': code, 'imm_code': imm_code, 43 'regs': ','.join(regs)}, opt_flags) 44 header_output = ImmDeclare.subst(iop) 45 decoder_output = ImmConstructor.subst(iop) 46 decode_block = BasicDecode.subst(iop) 47 exec_output = ImmExecute.subst(iop) 48}}; 49 |
50def format CUIOp(imm_code, code, *opt_flags) {{ 51 regs = ['_destRegIdx[0]','_srcRegIdx[0]'] 52 iop = InstObjParams(name, Name, 'ImmOp<uint64_t>', 53 {'code': code, 'imm_code': imm_code, 54 'regs': ','.join(regs)}, opt_flags) 55 header_output = ImmDeclare.subst(iop) 56 decoder_output = ImmConstructor.subst(iop) 57 decode_block = BasicDecode.subst(iop) 58 exec_output = ImmExecute.subst(iop) 59}}; 60 | |
61def format CompressedLoad(ldisp_code, memacc_code, 62 ea_code, mem_flags=[], inst_flags=[]) {{ 63 (header_output, decoder_output, decode_block, exec_output) = \ 64 LoadStoreBase(name, Name, ldisp_code, ea_code, memacc_code, mem_flags, 65 inst_flags, 'Load', exec_template_base='Load') 66}}; 67 68def format CompressedStore(sdisp_code, memacc_code, 69 ea_code, mem_flags=[], inst_flags=[]) {{ 70 (header_output, decoder_output, decode_block, exec_output) = \ 71 LoadStoreBase(name, Name, sdisp_code, ea_code, memacc_code, mem_flags, 72 inst_flags, 'Store', exec_template_base='Store') 73}}; | 50def format CompressedLoad(ldisp_code, memacc_code, 51 ea_code, mem_flags=[], inst_flags=[]) {{ 52 (header_output, decoder_output, decode_block, exec_output) = \ 53 LoadStoreBase(name, Name, ldisp_code, ea_code, memacc_code, mem_flags, 54 inst_flags, 'Load', exec_template_base='Load') 55}}; 56 57def format CompressedStore(sdisp_code, memacc_code, 58 ea_code, mem_flags=[], inst_flags=[]) {{ 59 (header_output, decoder_output, decode_block, exec_output) = \ 60 LoadStoreBase(name, Name, sdisp_code, ea_code, memacc_code, mem_flags, 61 inst_flags, 'Store', exec_template_base='Store') 62}}; |