1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are
9// met: redistributions of source code must retain the above copyright
10// notice, this list of conditions and the following disclaimer;
11// redistributions in binary form must reproduce the above copyright
12// notice, this list of conditions and the following disclaimer in the
13// documentation and/or other materials provided with the distribution;
14// neither the name of the copyright holders nor the names of its
15// contributors may be used to endorse or promote products derived from
16// this software without specific prior written permission.
17//
18// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29//
30// Authors: Alec Roelke
31def format CROp(code, *opt_flags) {{
32 iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags)
33 header_output = BasicDeclare.subst(iop)
34 decoder_output = BasicConstructor.subst(iop)
35 decode_block = BasicDecode.subst(iop)
36 exec_output = BasicExecute.subst(iop)
37}};
38
39def format CIOp(imm_code, code, imm_type='int64_t', *opt_flags) {{
40 regs = ['_destRegIdx[0]','_srcRegIdx[0]']
41 iop = InstObjParams(name, Name, 'ImmOp<%s>' % imm_type,
42 {'code': code, 'imm_code': imm_code,
43 'regs': ','.join(regs)}, opt_flags)
44 header_output = ImmDeclare.subst(iop)
45 decoder_output = ImmConstructor.subst(iop)
46 decode_block = BasicDecode.subst(iop)
47 exec_output = ImmExecute.subst(iop)
48}};
49
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are
9// met: redistributions of source code must retain the above copyright
10// notice, this list of conditions and the following disclaimer;
11// redistributions in binary form must reproduce the above copyright
12// notice, this list of conditions and the following disclaimer in the
13// documentation and/or other materials provided with the distribution;
14// neither the name of the copyright holders nor the names of its
15// contributors may be used to endorse or promote products derived from
16// this software without specific prior written permission.
17//
18// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29//
30// Authors: Alec Roelke
31def format CROp(code, *opt_flags) {{
32 iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags)
33 header_output = BasicDeclare.subst(iop)
34 decoder_output = BasicConstructor.subst(iop)
35 decode_block = BasicDecode.subst(iop)
36 exec_output = BasicExecute.subst(iop)
37}};
38
39def format CIOp(imm_code, code, imm_type='int64_t', *opt_flags) {{
40 regs = ['_destRegIdx[0]','_srcRegIdx[0]']
41 iop = InstObjParams(name, Name, 'ImmOp<%s>' % imm_type,
42 {'code': code, 'imm_code': imm_code,
43 'regs': ','.join(regs)}, opt_flags)
44 header_output = ImmDeclare.subst(iop)
45 decoder_output = ImmConstructor.subst(iop)
46 decode_block = BasicDecode.subst(iop)
47 exec_output = ImmExecute.subst(iop)
48}};
49
|
| 50def format CJOp(code, *opt_flags) {{
51 regs = ['_destRegIdx[0]', '_srcRegIdx[0]']
52 imm_code = """
53 imm = CJUMPIMM3TO1 << 1 |
54 CJUMPIMM4TO4 << 4 |
55 CJUMPIMM5TO5 << 5 |
56 CJUMPIMM6TO6 << 6 |
57 CJUMPIMM7TO7 << 7 |
58 CJUMPIMM9TO8 << 8 |
59 CJUMPIMM10TO10 << 10;
60 if (CJUMPIMMSIGN)
61 imm |= ~((int64_t)0x7FF);
62 """
63 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
64 {'code': code, 'imm_code': imm_code,
65 'regs': ','.join(regs)}, opt_flags)
66 header_output = BranchDeclare.subst(iop)
67 decoder_output = ImmConstructor.subst(iop)
68 decode_block = BasicDecode.subst(iop)
69 exec_output = BranchExecute.subst(iop)
70}};
71
|
50def format CBOp(code, *opt_flags) {{
51 imm_code = """
52 imm = CIMM5<2:1> << 1 |
53 CIMM3<1:0> << 3 |
54 CIMM5<0:0> << 5 |
55 CIMM5<4:3> << 6;
56 if (CIMM3<2:2> > 0)
57 imm |= ~((int64_t)0xFF);
58 """
59 regs = ['_srcRegIdx[0]','_srcRegIdx[1]']
60 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
61 {'code': code, 'imm_code': imm_code,
62 'regs': ','.join(regs)}, opt_flags)
63 header_output = BranchDeclare.subst(iop)
64 decoder_output = ImmConstructor.subst(iop)
65 decode_block = BasicDecode.subst(iop)
66 exec_output = BranchExecute.subst(iop)
67}};
68
69def format CompressedLoad(ldisp_code, memacc_code,
70 ea_code, mem_flags=[], inst_flags=[]) {{
71 (header_output, decoder_output, decode_block, exec_output) = \
72 LoadStoreBase(name, Name, ldisp_code, ea_code, memacc_code, mem_flags,
73 inst_flags, 'Load', exec_template_base='Load')
74}};
75
76def format CompressedStore(sdisp_code, memacc_code,
77 ea_code, mem_flags=[], inst_flags=[]) {{
78 (header_output, decoder_output, decode_block, exec_output) = \
79 LoadStoreBase(name, Name, sdisp_code, ea_code, memacc_code, mem_flags,
80 inst_flags, 'Store', exec_template_base='Store')
81}};
| 72def format CBOp(code, *opt_flags) {{
73 imm_code = """
74 imm = CIMM5<2:1> << 1 |
75 CIMM3<1:0> << 3 |
76 CIMM5<0:0> << 5 |
77 CIMM5<4:3> << 6;
78 if (CIMM3<2:2> > 0)
79 imm |= ~((int64_t)0xFF);
80 """
81 regs = ['_srcRegIdx[0]','_srcRegIdx[1]']
82 iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
83 {'code': code, 'imm_code': imm_code,
84 'regs': ','.join(regs)}, opt_flags)
85 header_output = BranchDeclare.subst(iop)
86 decoder_output = ImmConstructor.subst(iop)
87 decode_block = BasicDecode.subst(iop)
88 exec_output = BranchExecute.subst(iop)
89}};
90
91def format CompressedLoad(ldisp_code, memacc_code,
92 ea_code, mem_flags=[], inst_flags=[]) {{
93 (header_output, decoder_output, decode_block, exec_output) = \
94 LoadStoreBase(name, Name, ldisp_code, ea_code, memacc_code, mem_flags,
95 inst_flags, 'Load', exec_template_base='Load')
96}};
97
98def format CompressedStore(sdisp_code, memacc_code,
99 ea_code, mem_flags=[], inst_flags=[]) {{
100 (header_output, decoder_output, decode_block, exec_output) = \
101 LoadStoreBase(name, Name, sdisp_code, ea_code, memacc_code, mem_flags,
102 inst_flags, 'Store', exec_template_base='Store')
103}};
|