1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 RISC-V Foundation
4// Copyright (c) 2017 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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42 {'code': code, 'imm_code': imm_code,
43 'regs': ','.join(regs)}, opt_flags)
44 header_output = ImmDeclare.subst(iop)
45 decoder_output = ImmConstructor.subst(iop)
46 decode_block = BasicDecode.subst(iop)
47 exec_output = ImmExecute.subst(iop)
48}};
49
50def format CompressedLoad(ldisp_code, memacc_code,
51 ea_code, mem_flags=[], inst_flags=[]) {{
52 (header_output, decoder_output, decode_block, exec_output) = \
53 LoadStoreBase(name, Name, ldisp_code, ea_code, memacc_code, mem_flags,
54 inst_flags, 'Load', exec_template_base='Load')
55}};
56
57def format CompressedStore(sdisp_code, memacc_code,
58 ea_code, mem_flags=[], inst_flags=[]) {{
59 (header_output, decoder_output, decode_block, exec_output) = \
60 LoadStoreBase(name, Name, sdisp_code, ea_code, memacc_code, mem_flags,
61 inst_flags, 'Store', exec_template_base='Store')
62}};