amo.isa (12119:e9ef3ee3171d) amo.isa (12234:78ece221f9f5)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 Riscv Developers
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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218 flags[IsLastMicroop] = true;
219 flags[IsNonSpeculative] = true;
220 if (RL)
221 memAccessFlags = Request::RELEASE;
222 }
223}};
224
225def template StoreCondExecute {{
1// -*- mode:c++ -*-
2
3// Copyright (c) 2015 Riscv Developers
4// Copyright (c) 2016 The University of Virginia
5// All rights reserved.
6//
7// Redistribution and use in source and binary forms, with or without
8// modification, are permitted provided that the following conditions are

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218 flags[IsLastMicroop] = true;
219 flags[IsNonSpeculative] = true;
220 if (RL)
221 memAccessFlags = Request::RELEASE;
222 }
223}};
224
225def template StoreCondExecute {{
226 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
226 Fault %(class_name)s::execute(ExecContext *xc,
227 Trace::InstRecord *traceData) const
228 {
229 Addr EA;
230 Fault fault = NoFault;
231 uint64_t result;
232
233 %(op_decl)s;
234 %(op_rd)s;

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254 %(op_wb)s;
255 }
256
257 return fault;
258 }
259}};
260
261def template AtomicMemOpLoadExecute {{
227 Trace::InstRecord *traceData) const
228 {
229 Addr EA;
230 Fault fault = NoFault;
231 uint64_t result;
232
233 %(op_decl)s;
234 %(op_rd)s;

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254 %(op_wb)s;
255 }
256
257 return fault;
258 }
259}};
260
261def template AtomicMemOpLoadExecute {{
262 Fault %(class_name)s::%(class_name)sLoad::execute(CPU_EXEC_CONTEXT *xc,
262 Fault %(class_name)s::%(class_name)sLoad::execute(ExecContext *xc,
263 Trace::InstRecord *traceData) const
264 {
265 Addr EA;
266 Fault fault = NoFault;
267
268 %(op_decl)s;
269 %(op_rd)s;
270 %(ea_code)s;

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281 %(op_wb)s;
282 }
283
284 return fault;
285 }
286}};
287
288def template AtomicMemOpStoreExecute {{
263 Trace::InstRecord *traceData) const
264 {
265 Addr EA;
266 Fault fault = NoFault;
267
268 %(op_decl)s;
269 %(op_rd)s;
270 %(ea_code)s;

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281 %(op_wb)s;
282 }
283
284 return fault;
285 }
286}};
287
288def template AtomicMemOpStoreExecute {{
289 Fault %(class_name)s::%(class_name)sStore::execute(CPU_EXEC_CONTEXT *xc,
289 Fault %(class_name)s::%(class_name)sStore::execute(ExecContext *xc,
290 Trace::InstRecord *traceData) const
291 {
292 Addr EA;
293 Fault fault = NoFault;
294
295 %(op_decl)s;
296 %(op_rd)s;
297 %(ea_code)s;

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310 }
311
312 return fault;
313 }
314}};
315
316def template AtomicMemOpEACompExecute {{
317 Fault
290 Trace::InstRecord *traceData) const
291 {
292 Addr EA;
293 Fault fault = NoFault;
294
295 %(op_decl)s;
296 %(op_rd)s;
297 %(ea_code)s;

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310 }
311
312 return fault;
313 }
314}};
315
316def template AtomicMemOpEACompExecute {{
317 Fault
318 %(class_name)s::%(class_name)s%(op_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
318 %(class_name)s::%(class_name)s%(op_name)s::eaComp(ExecContext *xc,
319 Trace::InstRecord *traceData) const
320 {
321 Addr EA;
322 Fault fault = NoFault;
323
324 %(op_decl)s;
325 %(op_rd)s;
326 %(ea_code)s;
327
328 if (fault == NoFault) {
329 %(op_wb)s;
330 xc->setEA(EA);
331 }
332
333 return fault;
334 }
335}};
336
337def template AtomicMemOpLoadInitiateAcc {{
319 Trace::InstRecord *traceData) const
320 {
321 Addr EA;
322 Fault fault = NoFault;
323
324 %(op_decl)s;
325 %(op_rd)s;
326 %(ea_code)s;
327
328 if (fault == NoFault) {
329 %(op_wb)s;
330 xc->setEA(EA);
331 }
332
333 return fault;
334 }
335}};
336
337def template AtomicMemOpLoadInitiateAcc {{
338 Fault %(class_name)s::%(class_name)sLoad::initiateAcc(CPU_EXEC_CONTEXT *xc,
338 Fault %(class_name)s::%(class_name)sLoad::initiateAcc(ExecContext *xc,
339 Trace::InstRecord *traceData) const
340 {
341 Addr EA;
342 Fault fault = NoFault;
343
344 %(op_src_decl)s;
345 %(op_rd)s;
346 %(ea_code)s;
347
348 if (fault == NoFault) {
349 fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
350 }
351
352 return fault;
353 }
354}};
355
356def template AtomicMemOpStoreInitiateAcc {{
357 Fault %(class_name)s::%(class_name)sStore::initiateAcc(
339 Trace::InstRecord *traceData) const
340 {
341 Addr EA;
342 Fault fault = NoFault;
343
344 %(op_src_decl)s;
345 %(op_rd)s;
346 %(ea_code)s;
347
348 if (fault == NoFault) {
349 fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
350 }
351
352 return fault;
353 }
354}};
355
356def template AtomicMemOpStoreInitiateAcc {{
357 Fault %(class_name)s::%(class_name)sStore::initiateAcc(
358 CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
358 ExecContext *xc, Trace::InstRecord *traceData) const
359 {
360 Addr EA;
361 Fault fault = NoFault;
362
363 %(op_decl)s;
364 %(op_rd)s;
365 %(ea_code)s;
366

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377 %(op_wb)s;
378 }
379
380 return fault;
381 }
382}};
383
384def template StoreCondCompleteAcc {{
359 {
360 Addr EA;
361 Fault fault = NoFault;
362
363 %(op_decl)s;
364 %(op_rd)s;
365 %(ea_code)s;
366

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377 %(op_wb)s;
378 }
379
380 return fault;
381 }
382}};
383
384def template StoreCondCompleteAcc {{
385 Fault %(class_name)s::completeAcc(Packet *pkt, CPU_EXEC_CONTEXT *xc,
385 Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
386 Trace::InstRecord *traceData) const
387 {
388 Fault fault = NoFault;
389
390 %(op_dest_decl)s;
391
392 // RISC-V has the opposite convention gem5 has for success flags,
393 // so we invert the result here.

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402 }
403
404 return fault;
405 }
406}};
407
408def template AtomicMemOpLoadCompleteAcc {{
409 Fault %(class_name)s::%(class_name)sLoad::completeAcc(PacketPtr pkt,
386 Trace::InstRecord *traceData) const
387 {
388 Fault fault = NoFault;
389
390 %(op_dest_decl)s;
391
392 // RISC-V has the opposite convention gem5 has for success flags,
393 // so we invert the result here.

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402 }
403
404 return fault;
405 }
406}};
407
408def template AtomicMemOpLoadCompleteAcc {{
409 Fault %(class_name)s::%(class_name)sLoad::completeAcc(PacketPtr pkt,
410 CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
410 ExecContext *xc, Trace::InstRecord *traceData) const
411 {
412 Fault fault = NoFault;
413
414 %(op_decl)s;
415 %(op_rd)s;
416
417 getMem(pkt, Mem, traceData);
418

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425 }
426
427 return fault;
428 }
429}};
430
431def template AtomicMemOpStoreCompleteAcc {{
432 Fault %(class_name)s::%(class_name)sStore::completeAcc(PacketPtr pkt,
411 {
412 Fault fault = NoFault;
413
414 %(op_decl)s;
415 %(op_rd)s;
416
417 getMem(pkt, Mem, traceData);
418

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425 }
426
427 return fault;
428 }
429}};
430
431def template AtomicMemOpStoreCompleteAcc {{
432 Fault %(class_name)s::%(class_name)sStore::completeAcc(PacketPtr pkt,
433 CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
433 ExecContext *xc, Trace::InstRecord *traceData) const
434 {
435 return NoFault;
436 }
437}};
438
439def format LoadReserved(memacc_code, postacc_code={{ }}, ea_code={{EA = Rs1;}},
440 mem_flags=[], inst_flags=[]) {{
441 mem_flags = makeList(mem_flags)

--- 63 unchanged lines hidden --- 		434 {
435 return NoFault;
436 }
437}};
438
439def format LoadReserved(memacc_code, postacc_code={{ }}, ea_code={{EA = Rs1;}},
440 mem_flags=[], inst_flags=[]) {{
441 mem_flags = makeList(mem_flags)

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