isa.hh (12119:e9ef3ee3171d) | isa.hh (12334:e0ab29a34764) |
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1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * Copyright (c) 2009 The University of Edinburgh 4 * Copyright (c) 2014 Sven Karlsson 5 * Copyright (c) 2016 RISC-V Foundation 6 * Copyright (c) 2016 The University of Virginia 7 * All rights reserved. 8 * --- 29 unchanged lines hidden (view full) --- 38#ifndef __ARCH_RISCV_ISA_HH__ 39#define __ARCH_RISCV_ISA_HH__ 40 41#include <map> 42#include <string> 43 44#include "arch/riscv/registers.hh" 45#include "arch/riscv/types.hh" | 1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * Copyright (c) 2009 The University of Edinburgh 4 * Copyright (c) 2014 Sven Karlsson 5 * Copyright (c) 2016 RISC-V Foundation 6 * Copyright (c) 2016 The University of Virginia 7 * All rights reserved. 8 * --- 29 unchanged lines hidden (view full) --- 38#ifndef __ARCH_RISCV_ISA_HH__ 39#define __ARCH_RISCV_ISA_HH__ 40 41#include <map> 42#include <string> 43 44#include "arch/riscv/registers.hh" 45#include "arch/riscv/types.hh" |
46#include "base/misc.hh" | 46#include "base/logging.hh" |
47#include "cpu/reg_class.hh" 48#include "sim/sim_object.hh" 49 50struct RiscvISAParams; 51class ThreadContext; 52class Checkpoint; 53class EventManager; 54 --- 83 unchanged lines hidden --- | 47#include "cpu/reg_class.hh" 48#include "sim/sim_object.hh" 49 50struct RiscvISAParams; 51class ThreadContext; 52class Checkpoint; 53class EventManager; 54 --- 83 unchanged lines hidden --- |