isa.hh (11963:3fb6bb58e6a4) isa.hh (12106:7784fac1b159)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * Copyright (c) 2009 The University of Edinburgh
4 * Copyright (c) 2014 Sven Karlsson
5 * Copyright (c) 2016 RISC-V Foundation
6 * Copyright (c) 2016 The University of Virginia
7 * All rights reserved.
8 *

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39#define __ARCH_RISCV_ISA_HH__
40
41#include <map>
42#include <string>
43
44#include "arch/riscv/registers.hh"
45#include "arch/riscv/types.hh"
46#include "base/misc.hh"
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * Copyright (c) 2009 The University of Edinburgh
4 * Copyright (c) 2014 Sven Karlsson
5 * Copyright (c) 2016 RISC-V Foundation
6 * Copyright (c) 2016 The University of Virginia
7 * All rights reserved.
8 *

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39#define __ARCH_RISCV_ISA_HH__
40
41#include <map>
42#include <string>
43
44#include "arch/riscv/registers.hh"
45#include "arch/riscv/types.hh"
46#include "base/misc.hh"
47#include "cpu/reg_class.hh"
47#include "sim/sim_object.hh"
48
49struct RiscvISAParams;
50class ThreadContext;
51class Checkpoint;
52class EventManager;
53
54namespace RiscvISA

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73 readMiscReg(int misc_reg, ThreadContext *tc);
74
75 void
76 setMiscRegNoEffect(int misc_reg, const MiscReg &val);
77
78 void
79 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
80
48#include "sim/sim_object.hh"
49
50struct RiscvISAParams;
51class ThreadContext;
52class Checkpoint;
53class EventManager;
54
55namespace RiscvISA

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74 readMiscReg(int misc_reg, ThreadContext *tc);
75
76 void
77 setMiscRegNoEffect(int misc_reg, const MiscReg &val);
78
79 void
80 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
81
82 RegId
83 flattenRegId(const RegId &regId) const
84 {
85 return regId;
86 }
87
81 int
82 flattenIntIndex(int reg) const
83 {
84 return reg;
85 }
86
87 int
88 flattenFloatIndex(int reg) const

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89 flattenIntIndex(int reg) const
90 {
91 return reg;
92 }
93
94 int
95 flattenFloatIndex(int reg) const

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