1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * Copyright (c) 2009 The University of Edinburgh 4 * Copyright (c) 2014 Sven Karlsson 5 * Copyright (c) 2016 RISC-V Foundation 6 * Copyright (c) 2016 The University of Virginia 7 * All rights reserved. 8 * --- 70 unchanged lines hidden (view full) --- 79 void setMiscRegNoEffect(int misc_reg, MiscReg val); 80 void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc); 81 82 RegId flattenRegId(const RegId ®Id) const { return regId; } 83 int flattenIntIndex(int reg) const { return reg; } 84 int flattenFloatIndex(int reg) const { return reg; } 85 int flattenVecIndex(int reg) const { return reg; } 86 int flattenVecElemIndex(int reg) const { return reg; } |
87 int flattenVecPredIndex(int reg) const { return reg; } |
88 int flattenCCIndex(int reg) const { return reg; } 89 int flattenMiscIndex(int reg) const { return reg; } 90 91 void startup(ThreadContext *tc) {} 92 93 /// Explicitly import the otherwise hidden startup 94 using SimObject::startup; 95 96 const Params *params() const; 97 98 ISA(Params *p); 99}; 100 101} // namespace RiscvISA 102 103#endif // __ARCH_RISCV_ISA_HH__ |