isa.hh (13610:5d5404ac6288) isa.hh (13612:12ae022f3a30)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * Copyright (c) 2009 The University of Edinburgh
4 * Copyright (c) 2014 Sven Karlsson
5 * Copyright (c) 2016 RISC-V Foundation
6 * Copyright (c) 2016 The University of Virginia
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions are
11 * met: redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer;
13 * redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution;
16 * neither the name of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * Authors: Gabe Black
33 * Timothy M. Jones
34 * Sven Karlsson
35 * Alec Roelke
36 */
37
38#ifndef __ARCH_RISCV_ISA_HH__
39#define __ARCH_RISCV_ISA_HH__
40
41#include <map>
42#include <string>
43
44#include "arch/riscv/registers.hh"
45#include "arch/riscv/types.hh"
46#include "base/bitfield.hh"
47#include "base/logging.hh"
48#include "cpu/reg_class.hh"
49#include "sim/sim_object.hh"
50
51struct RiscvISAParams;
52class ThreadContext;
53class Checkpoint;
54class EventManager;
55
56namespace RiscvISA
57{
58
59enum PrivilegeMode {
60 PRV_U = 0,
61 PRV_S = 1,
62 PRV_M = 3
63};
64
65class ISA : public SimObject
66{
67 protected:
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * Copyright (c) 2009 The University of Edinburgh
4 * Copyright (c) 2014 Sven Karlsson
5 * Copyright (c) 2016 RISC-V Foundation
6 * Copyright (c) 2016 The University of Virginia
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions are
11 * met: redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer;
13 * redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution;
16 * neither the name of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * Authors: Gabe Black
33 * Timothy M. Jones
34 * Sven Karlsson
35 * Alec Roelke
36 */
37
38#ifndef __ARCH_RISCV_ISA_HH__
39#define __ARCH_RISCV_ISA_HH__
40
41#include <map>
42#include <string>
43
44#include "arch/riscv/registers.hh"
45#include "arch/riscv/types.hh"
46#include "base/bitfield.hh"
47#include "base/logging.hh"
48#include "cpu/reg_class.hh"
49#include "sim/sim_object.hh"
50
51struct RiscvISAParams;
52class ThreadContext;
53class Checkpoint;
54class EventManager;
55
56namespace RiscvISA
57{
58
59enum PrivilegeMode {
60 PRV_U = 0,
61 PRV_S = 1,
62 PRV_M = 3
63};
64
65class ISA : public SimObject
66{
67 protected:
68 std::vector<MiscReg> miscRegFile;
68 std::vector<RegVal> miscRegFile;
69
70 bool hpmCounterEnabled(int counter) const;
71
72 public:
73 typedef RiscvISAParams Params;
74
75 void clear();
76
69
70 bool hpmCounterEnabled(int counter) const;
71
72 public:
73 typedef RiscvISAParams Params;
74
75 void clear();
76
77 MiscReg readMiscRegNoEffect(int misc_reg) const;
78 MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
79 void setMiscRegNoEffect(int misc_reg, MiscReg val);
80 void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc);
77 RegVal readMiscRegNoEffect(int misc_reg) const;
78 RegVal readMiscReg(int misc_reg, ThreadContext *tc);
79 void setMiscRegNoEffect(int misc_reg, RegVal val);
80 void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);
81
82 RegId flattenRegId(const RegId &regId) const { return regId; }
83 int flattenIntIndex(int reg) const { return reg; }
84 int flattenFloatIndex(int reg) const { return reg; }
85 int flattenVecIndex(int reg) const { return reg; }
86 int flattenVecElemIndex(int reg) const { return reg; }
87 int flattenVecPredIndex(int reg) const { return reg; }
88 int flattenCCIndex(int reg) const { return reg; }
89 int flattenMiscIndex(int reg) const { return reg; }
90
91 void startup(ThreadContext *tc) {}
92
93 /// Explicitly import the otherwise hidden startup
94 using SimObject::startup;
95
96 const Params *params() const;
97
98 ISA(Params *p);
99};
100
101} // namespace RiscvISA
102
103#endif // __ARCH_RISCV_ISA_HH__
81
82 RegId flattenRegId(const RegId &regId) const { return regId; }
83 int flattenIntIndex(int reg) const { return reg; }
84 int flattenFloatIndex(int reg) const { return reg; }
85 int flattenVecIndex(int reg) const { return reg; }
86 int flattenVecElemIndex(int reg) const { return reg; }
87 int flattenVecPredIndex(int reg) const { return reg; }
88 int flattenCCIndex(int reg) const { return reg; }
89 int flattenMiscIndex(int reg) const { return reg; }
90
91 void startup(ThreadContext *tc) {}
92
93 /// Explicitly import the otherwise hidden startup
94 using SimObject::startup;
95
96 const Params *params() const;
97
98 ISA(Params *p);
99};
100
101} // namespace RiscvISA
102
103#endif // __ARCH_RISCV_ISA_HH__