isa.cc (13612:12ae022f3a30) isa.cc (13935:02b924bd5ee9)
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 98 unchanged lines hidden (view full) ---

107 miscRegFile[misc_reg]);
108 return miscRegFile[misc_reg];
109}
110
111RegVal
112ISA::readMiscReg(int misc_reg, ThreadContext *tc)
113{
114 switch (misc_reg) {
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 98 unchanged lines hidden (view full) ---

107 miscRegFile[misc_reg]);
108 return miscRegFile[misc_reg];
109}
110
111RegVal
112ISA::readMiscReg(int misc_reg, ThreadContext *tc)
113{
114 switch (misc_reg) {
115 case MISCREG_HARTID:
116 return tc->contextId();
115 case MISCREG_CYCLE:
116 if (hpmCounterEnabled(MISCREG_CYCLE)) {
117 DPRINTF(RiscvMisc, "Cycle counter at: %llu.\n",
118 tc->getCpuPtr()->curCycle());
119 return tc->getCpuPtr()->curCycle();
120 } else {
121 warn("Cycle counter disabled.\n");
122 return 0;

--- 81 unchanged lines hidden --- 		117 case MISCREG_CYCLE:
118 if (hpmCounterEnabled(MISCREG_CYCLE)) {
119 DPRINTF(RiscvMisc, "Cycle counter at: %llu.\n",
120 tc->getCpuPtr()->curCycle());
121 return tc->getCpuPtr()->curCycle();
122 } else {
123 warn("Cycle counter disabled.\n");
124 return 0;

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