isa.cc (13582:989577bf6abc) isa.cc (13612:12ae022f3a30)
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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90 break;
91 default:
92 panic("Unknown privilege level %d\n", miscRegFile[MISCREG_PRV]);
93 return false;
94 }
95 return (miscRegFile[counteren] & (1ULL << (hpmcounter))) > 0;
96}
97
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 81 unchanged lines hidden (view full) ---

90 break;
91 default:
92 panic("Unknown privilege level %d\n", miscRegFile[MISCREG_PRV]);
93 return false;
94 }
95 return (miscRegFile[counteren] & (1ULL << (hpmcounter))) > 0;
96}
97
98MiscReg
98RegVal
99ISA::readMiscRegNoEffect(int misc_reg) const
100{
101 if (misc_reg > NumMiscRegs || misc_reg < 0) {
102 // Illegal CSR
103 panic("Illegal CSR index %#x\n", misc_reg);
104 return -1;
105 }
106 DPRINTF(RiscvMisc, "Reading MiscReg %d: %#llx.\n", misc_reg,
107 miscRegFile[misc_reg]);
108 return miscRegFile[misc_reg];
109}
110
99ISA::readMiscRegNoEffect(int misc_reg) const
100{
101 if (misc_reg > NumMiscRegs || misc_reg < 0) {
102 // Illegal CSR
103 panic("Illegal CSR index %#x\n", misc_reg);
104 return -1;
105 }
106 DPRINTF(RiscvMisc, "Reading MiscReg %d: %#llx.\n", misc_reg,
107 miscRegFile[misc_reg]);
108 return miscRegFile[misc_reg];
109}
110
111MiscReg
111RegVal
112ISA::readMiscReg(int misc_reg, ThreadContext *tc)
113{
114 switch (misc_reg) {
115 case MISCREG_CYCLE:
116 if (hpmCounterEnabled(MISCREG_CYCLE)) {
117 DPRINTF(RiscvMisc, "Cycle counter at: %llu.\n",
118 tc->getCpuPtr()->curCycle());
119 return tc->getCpuPtr()->curCycle();

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159 return 0;
160 }
161 }
162 return readMiscRegNoEffect(misc_reg);
163 }
164}
165
166void
112ISA::readMiscReg(int misc_reg, ThreadContext *tc)
113{
114 switch (misc_reg) {
115 case MISCREG_CYCLE:
116 if (hpmCounterEnabled(MISCREG_CYCLE)) {
117 DPRINTF(RiscvMisc, "Cycle counter at: %llu.\n",
118 tc->getCpuPtr()->curCycle());
119 return tc->getCpuPtr()->curCycle();

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159 return 0;
160 }
161 }
162 return readMiscRegNoEffect(misc_reg);
163 }
164}
165
166void
167ISA::setMiscRegNoEffect(int misc_reg, MiscReg val)
167ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
168{
169 if (misc_reg > NumMiscRegs || misc_reg < 0) {
170 // Illegal CSR
171 panic("Illegal CSR index %#x\n", misc_reg);
172 }
173 DPRINTF(RiscvMisc, "Setting MiscReg %d to %#x.\n", misc_reg, val);
174 miscRegFile[misc_reg] = val;
175}
176
177void
168{
169 if (misc_reg > NumMiscRegs || misc_reg < 0) {
170 // Illegal CSR
171 panic("Illegal CSR index %#x\n", misc_reg);
172 }
173 DPRINTF(RiscvMisc, "Setting MiscReg %d to %#x.\n", misc_reg, val);
174 miscRegFile[misc_reg] = val;
175}
176
177void
178ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc)
178ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
179{
180 if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) {
181 // Ignore writes to HPM counters for now
182 warn("Ignoring write to %s.\n", CSRData.at(misc_reg).name);
183 } else {
184 switch (misc_reg) {
185 case MISCREG_IP:
186 return tc->getCpuPtr()->getInterruptController(tc->threadId())

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180 if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) {
181 // Ignore writes to HPM counters for now
182 warn("Ignoring write to %s.\n", CSRData.at(misc_reg).name);
183 } else {
184 switch (misc_reg) {
185 case MISCREG_IP:
186 return tc->getCpuPtr()->getInterruptController(tc->threadId())

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