isa.cc (12695:3df197da6069) | isa.cc (13548:b76f99d052bb) |
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1/* 2 * Copyright (c) 2016 RISC-V Foundation 3 * Copyright (c) 2016 The University of Virginia 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 125 unchanged lines hidden (view full) --- 134 if (hpmCounterEnabled(MISCREG_INSTRET)) { 135 DPRINTF(RiscvMisc, "Instruction counter at: %llu.\n", 136 tc->getCpuPtr()->totalInsts()); 137 return tc->getCpuPtr()->totalInsts(); 138 } else { 139 warn("Instruction counter disabled.\n"); 140 return 0; 141 } | 1/* 2 * Copyright (c) 2016 RISC-V Foundation 3 * Copyright (c) 2016 The University of Virginia 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 125 unchanged lines hidden (view full) --- 134 if (hpmCounterEnabled(MISCREG_INSTRET)) { 135 DPRINTF(RiscvMisc, "Instruction counter at: %llu.\n", 136 tc->getCpuPtr()->totalInsts()); 137 return tc->getCpuPtr()->totalInsts(); 138 } else { 139 warn("Instruction counter disabled.\n"); 140 return 0; 141 } |
142 case MISCREG_IP: 143 return tc->getCpuPtr()->getInterruptController(tc->threadId()) 144 ->readIP(); 145 case MISCREG_IE: 146 return tc->getCpuPtr()->getInterruptController(tc->threadId()) 147 ->readIE(); |
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142 default: 143 // Try reading HPM counters 144 // As a placeholder, all HPM counters are just cycle counters 145 if (misc_reg >= MISCREG_HPMCOUNTER03 && 146 misc_reg <= MISCREG_HPMCOUNTER31) { 147 if (hpmCounterEnabled(misc_reg)) { 148 DPRINTF(RiscvMisc, "HPM counter %d: %llu.\n", 149 misc_reg - MISCREG_CYCLE, tc->getCpuPtr()->curCycle()); --- 20 unchanged lines hidden (view full) --- 170 171void 172ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 173{ 174 if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) { 175 // Ignore writes to HPM counters for now 176 warn("Ignoring write to %s.\n", CSRData.at(misc_reg).name); 177 } else { | 148 default: 149 // Try reading HPM counters 150 // As a placeholder, all HPM counters are just cycle counters 151 if (misc_reg >= MISCREG_HPMCOUNTER03 && 152 misc_reg <= MISCREG_HPMCOUNTER31) { 153 if (hpmCounterEnabled(misc_reg)) { 154 DPRINTF(RiscvMisc, "HPM counter %d: %llu.\n", 155 misc_reg - MISCREG_CYCLE, tc->getCpuPtr()->curCycle()); --- 20 unchanged lines hidden (view full) --- 176 177void 178ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 179{ 180 if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) { 181 // Ignore writes to HPM counters for now 182 warn("Ignoring write to %s.\n", CSRData.at(misc_reg).name); 183 } else { |
178 setMiscRegNoEffect(misc_reg, val); | 184 switch (misc_reg) { 185 case MISCREG_IP: 186 return tc->getCpuPtr()->getInterruptController(tc->threadId()) 187 ->setIP(val); 188 case MISCREG_IE: 189 return tc->getCpuPtr()->getInterruptController(tc->threadId()) 190 ->setIE(val); 191 default: 192 setMiscRegNoEffect(misc_reg, val); 193 } |
179 } 180} 181 182} 183 184RiscvISA::ISA * 185RiscvISAParams::create() 186{ 187 return new RiscvISA::ISA(this); 188} | 194 } 195} 196 197} 198 199RiscvISA::ISA * 200RiscvISAParams::create() 201{ 202 return new RiscvISA::ISA(this); 203} |