interrupts.hh (13625:8ca74a22ab30) | interrupts.hh (13628:332f730a1855) |
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1/* 2 * Copyright (c) 2011 Google 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 117 unchanged lines hidden (view full) --- 126 } 127 128 uint64_t readIP() const { return (uint64_t)ip.to_ulong(); } 129 uint64_t readIE() const { return (uint64_t)ie.to_ulong(); } 130 void setIP(const uint64_t& val) { ip = val; } 131 void setIE(const uint64_t& val) { ie = val; } 132 133 void | 1/* 2 * Copyright (c) 2011 Google 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 117 unchanged lines hidden (view full) --- 126 } 127 128 uint64_t readIP() const { return (uint64_t)ip.to_ulong(); } 129 uint64_t readIE() const { return (uint64_t)ie.to_ulong(); } 130 void setIP(const uint64_t& val) { ip = val; } 131 void setIE(const uint64_t& val) { ie = val; } 132 133 void |
134 serialize(CheckpointOut &cp) | 134 serialize(CheckpointOut &cp) const |
135 { 136 SERIALIZE_SCALAR(ip.to_ulong()); 137 SERIALIZE_SCALAR(ie.to_ulong()); 138 } 139 140 void 141 unserialize(CheckpointIn &cp) 142 { 143 long reg; 144 UNSERIALIZE_SCALAR(reg); 145 ip = reg; 146 UNSERIALIZE_SCALAR(reg); 147 ie = reg; 148 } 149}; 150 151} // namespace RiscvISA 152 153#endif // __ARCH_RISCV_INTERRUPT_HH__ | 135 { 136 SERIALIZE_SCALAR(ip.to_ulong()); 137 SERIALIZE_SCALAR(ie.to_ulong()); 138 } 139 140 void 141 unserialize(CheckpointIn &cp) 142 { 143 long reg; 144 UNSERIALIZE_SCALAR(reg); 145 ip = reg; 146 UNSERIALIZE_SCALAR(reg); 147 ie = reg; 148 } 149}; 150 151} // namespace RiscvISA 152 153#endif // __ARCH_RISCV_INTERRUPT_HH__ |