interrupts.hh (12334:e0ab29a34764) interrupts.hh (12808:f275fd1244ce)
1/*
2 * Copyright (c) 2011 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_RISCV_INTERRUPT_HH__
32#define __ARCH_RISCV_INTERRUPT_HH__
33
34#include "base/logging.hh"
1/*
2 * Copyright (c) 2011 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 18 unchanged lines hidden (view full) ---

27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_RISCV_INTERRUPT_HH__
32#define __ARCH_RISCV_INTERRUPT_HH__
33
34#include "base/logging.hh"
35#include "cpu/thread_context.hh"
35#include "params/RiscvInterrupts.hh"
36#include "sim/sim_object.hh"
37
38class BaseCPU;
39class ThreadContext;
40
41namespace RiscvISA {
42

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73 clear(int int_num, int index)
74 {
75 panic("Interrupts::clear not implemented.\n");
76 }
77
78 void
79 clearAll()
80 {
36#include "params/RiscvInterrupts.hh"
37#include "sim/sim_object.hh"
38
39class BaseCPU;
40class ThreadContext;
41
42namespace RiscvISA {
43

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74 clear(int int_num, int index)
75 {
76 panic("Interrupts::clear not implemented.\n");
77 }
78
79 void
80 clearAll()
81 {
81 panic("Interrupts::clearAll not implemented.\n");
82 warn_once("Interrupts::clearAll not implemented.\n");
82 }
83
84 bool
85 checkInterrupts(ThreadContext *tc) const
86 {
83 }
84
85 bool
86 checkInterrupts(ThreadContext *tc) const
87 {
87 panic("Interrupts::checkInterrupts not implemented.\n");
88 warn_once("Interrupts::checkInterrupts just rudimentary implemented");
89 /**
90 * read the machine interrupt register in order to check if interrupts
91 * are pending
92 * should be sufficient for now, as interrupts
93 * are not implemented at all
94 */
95 if (tc->readMiscReg(MISCREG_IP))
96 return true;
97
98 return false;
88 }
89
90 Fault
91 getInterrupt(ThreadContext *tc)
92 {
93 assert(checkInterrupts(tc));
94 panic("Interrupts::getInterrupt not implemented.\n");
95 }

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100
101 Fault
102 getInterrupt(ThreadContext *tc)
103 {
104 assert(checkInterrupts(tc));
105 panic("Interrupts::getInterrupt not implemented.\n");
106 }

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