interrupts.hh (11800:54436a1784dc) | interrupts.hh (12334:e0ab29a34764) |
---|---|
1/* 2 * Copyright (c) 2011 Google 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __ARCH_RISCV_INTERRUPT_HH__ 32#define __ARCH_RISCV_INTERRUPT_HH__ 33 | 1/* 2 * Copyright (c) 2011 Google 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __ARCH_RISCV_INTERRUPT_HH__ 32#define __ARCH_RISCV_INTERRUPT_HH__ 33 |
34#include "base/misc.hh" | 34#include "base/logging.hh" |
35#include "params/RiscvInterrupts.hh" 36#include "sim/sim_object.hh" 37 38class BaseCPU; 39class ThreadContext; 40 41namespace RiscvISA { 42 --- 65 unchanged lines hidden --- | 35#include "params/RiscvInterrupts.hh" 36#include "sim/sim_object.hh" 37 38class BaseCPU; 39class ThreadContext; 40 41namespace RiscvISA { 42 --- 65 unchanged lines hidden --- |