1/* 2 * Copyright (c) 2015 RISC-V Foundation 3 * Copyright (c) 2016 The University of Virginia 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 61 unchanged lines hidden (view full) --- 70 OpClass __opClass) : 71 RiscvStaticInst(mnem, _machInst, __opClass) 72 { 73 flags[IsMacroop] = true; 74 } 75 76 ~RiscvMacroInst() { microops.clear(); } 77 |
78 StaticInstPtr 79 fetchMicroop(MicroPC upc) const override 80 { 81 return microops[upc]; 82 } |
83 84 Fault |
85 initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const override |
86 { 87 panic("Tried to execute a macroop directly!\n"); 88 } 89 90 Fault 91 completeAcc(PacketPtr pkt, ExecContext *xc, |
92 Trace::InstRecord *traceData) const override |
93 { 94 panic("Tried to execute a macroop directly!\n"); 95 } 96 97 Fault |
98 execute(ExecContext *xc, Trace::InstRecord *traceData) const override |
99 { 100 panic("Tried to execute a macroop directly!\n"); 101 } 102}; 103 104/** 105 * Base class for all RISC-V Microops 106 */ --- 16 unchanged lines hidden --- |