1/*
2 * Copyright (c) 2015 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Maxwell Walter
30 * Alec Roelke
31 */
32
33#ifndef __ARCH_RISCV_STATIC_INST_HH__
34#define __ARCH_RISCV_STATIC_INST_HH__
35
36#include <string>
37
38#include "arch/riscv/types.hh"
39#include "cpu/exec_context.hh"
40#include "cpu/static_inst.hh"
41#include "mem/packet.hh"
42
43namespace RiscvISA
44{
45
46/**
47 * Base class for all RISC-V static instructions.
48 */
49class RiscvStaticInst : public StaticInst
50{
51 protected:
52 using StaticInst::StaticInst;
53
54 virtual std::string
55 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
56
57 public:
58 void advancePC(PCState &pc) const { pc.advance(); }
| 1/*
2 * Copyright (c) 2015 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Maxwell Walter
30 * Alec Roelke
31 */
32
33#ifndef __ARCH_RISCV_STATIC_INST_HH__
34#define __ARCH_RISCV_STATIC_INST_HH__
35
36#include <string>
37
38#include "arch/riscv/types.hh"
39#include "cpu/exec_context.hh"
40#include "cpu/static_inst.hh"
41#include "mem/packet.hh"
42
43namespace RiscvISA
44{
45
46/**
47 * Base class for all RISC-V static instructions.
48 */
49class RiscvStaticInst : public StaticInst
50{
51 protected:
52 using StaticInst::StaticInst;
53
54 virtual std::string
55 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
56
57 public:
58 void advancePC(PCState &pc) const { pc.advance(); }
|
59};
60
61/**
62 * Base class for all RISC-V Macroops
63 */
64class RiscvMacroInst : public RiscvStaticInst
65{
66 protected:
67 std::vector<StaticInstPtr> microops;
68
69 RiscvMacroInst(const char *mnem, ExtMachInst _machInst,
70 OpClass __opClass) :
71 RiscvStaticInst(mnem, _machInst, __opClass)
72 {
73 flags[IsMacroop] = true;
74 }
75
76 ~RiscvMacroInst() { microops.clear(); }
77
78 StaticInstPtr
79 fetchMicroop(MicroPC upc) const override
80 {
81 return microops[upc];
82 }
83
84 Fault
85 initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const override
86 {
87 panic("Tried to execute a macroop directly!\n");
88 }
89
90 Fault
91 completeAcc(PacketPtr pkt, ExecContext *xc,
92 Trace::InstRecord *traceData) const override
93 {
94 panic("Tried to execute a macroop directly!\n");
95 }
96
97 Fault
98 execute(ExecContext *xc, Trace::InstRecord *traceData) const override
99 {
100 panic("Tried to execute a macroop directly!\n");
101 }
102};
103
104/**
105 * Base class for all RISC-V Microops
106 */
107class RiscvMicroInst : public RiscvStaticInst
108{
109 protected:
110 RiscvMicroInst(const char *mnem, ExtMachInst _machInst,
111 OpClass __opClass) :
112 RiscvStaticInst(mnem, _machInst, __opClass)
113 {
114 flags[IsMicroop] = true;
115 }
116
117 void advancePC(PCState &pcState) const;
118};
119
120}
121
122#endif // __ARCH_RISCV_STATIC_INST_HH__
| 65};
66
67/**
68 * Base class for all RISC-V Macroops
69 */
70class RiscvMacroInst : public RiscvStaticInst
71{
72 protected:
73 std::vector<StaticInstPtr> microops;
74
75 RiscvMacroInst(const char *mnem, ExtMachInst _machInst,
76 OpClass __opClass) :
77 RiscvStaticInst(mnem, _machInst, __opClass)
78 {
79 flags[IsMacroop] = true;
80 }
81
82 ~RiscvMacroInst() { microops.clear(); }
83
84 StaticInstPtr
85 fetchMicroop(MicroPC upc) const override
86 {
87 return microops[upc];
88 }
89
90 Fault
91 initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const override
92 {
93 panic("Tried to execute a macroop directly!\n");
94 }
95
96 Fault
97 completeAcc(PacketPtr pkt, ExecContext *xc,
98 Trace::InstRecord *traceData) const override
99 {
100 panic("Tried to execute a macroop directly!\n");
101 }
102
103 Fault
104 execute(ExecContext *xc, Trace::InstRecord *traceData) const override
105 {
106 panic("Tried to execute a macroop directly!\n");
107 }
108};
109
110/**
111 * Base class for all RISC-V Microops
112 */
113class RiscvMicroInst : public RiscvStaticInst
114{
115 protected:
116 RiscvMicroInst(const char *mnem, ExtMachInst _machInst,
117 OpClass __opClass) :
118 RiscvStaticInst(mnem, _machInst, __opClass)
119 {
120 flags[IsMicroop] = true;
121 }
122
123 void advancePC(PCState &pcState) const;
124};
125
126}
127
128#endif // __ARCH_RISCV_STATIC_INST_HH__
|