1/*
2 * Copyright (c) 2015 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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46/**
47 * Base class for all RISC-V static instructions.
48 */
49class RiscvStaticInst : public StaticInst
50{
51 protected:
52 using StaticInst::StaticInst;
53
54 virtual std::string
55 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
56
57 public:
58 void advancePC(PCState &pc) const { pc.advance(); }
59
60 size_t
61 asBytes(void *buf, size_t size) override
62 {
63 return simpleAsBytes(buf, size, machInst);
64 }
65};
66

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115 protected:
116 RiscvMicroInst(const char *mnem, ExtMachInst _machInst,
117 OpClass __opClass) :
118 RiscvStaticInst(mnem, _machInst, __opClass)
119 {
120 flags[IsMicroop] = true;
121 }
122
123 void advancePC(PCState &pcState) const;
124};
125
126}
127
128#endif // __ARCH_RISCV_STATIC_INST_HH__