1/*
2 * Copyright (c) 2015 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
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51 protected:
52 using StaticInst::StaticInst;
53
54 virtual std::string
55 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
56
57 public:
58 void advancePC(PCState &pc) const { pc.advance(); }
59};
60
61/**
62 * Base class for all RISC-V Macroops
63 */
64class RiscvMacroInst : public RiscvStaticInst
65{
66 protected:
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2 * Copyright (c) 2015 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
--- 42 unchanged lines hidden (view full) ---
51 protected:
52 using StaticInst::StaticInst;
53
54 virtual std::string
55 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
56
57 public:
58 void advancePC(PCState &pc) const { pc.advance(); }
59};
60
61/**
62 * Base class for all RISC-V Macroops
63 */
64class RiscvMacroInst : public RiscvStaticInst
65{
66 protected:
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