1/*
2 * Copyright (c) 2015 RISC-V Foundation
3 * Copyright (c) 2017 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Alec Roelke
30 */
31
32#ifndef __ARCH_RISCV_INSTS_AMO_HH__
33#define __ARCH_RISCV_INSTS_AMO_HH__
34
35#include <string>
36
37#include "arch/riscv/insts/mem.hh"
38#include "arch/riscv/insts/static_inst.hh"
39#include "cpu/static_inst.hh"
40
41namespace RiscvISA
42{
43
| 1/*
2 * Copyright (c) 2015 RISC-V Foundation
3 * Copyright (c) 2017 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Alec Roelke
30 */
31
32#ifndef __ARCH_RISCV_INSTS_AMO_HH__
33#define __ARCH_RISCV_INSTS_AMO_HH__
34
35#include <string>
36
37#include "arch/riscv/insts/mem.hh"
38#include "arch/riscv/insts/static_inst.hh"
39#include "cpu/static_inst.hh"
40
41namespace RiscvISA
42{
43
|
44class LoadReserved : public MemInst
| 44// memfence micro instruction
45class MemFenceMicro : public RiscvMicroInst
|
45{
| 46{
|
| 47 public:
48 MemFenceMicro(ExtMachInst _machInst, OpClass __opClass)
49 : RiscvMicroInst("fence", _machInst, __opClass)
50 { }
|
46 protected:
| 51 protected:
|
47 using MemInst::MemInst;
| 52 using RiscvMicroInst::RiscvMicroInst;
|
48
| 53
|
| 54 Fault execute(ExecContext *, Trace::InstRecord *) const override;
|
49 std::string generateDisassembly(
50 Addr pc, const SymbolTable *symtab) const override;
51};
52
| 55 std::string generateDisassembly(
56 Addr pc, const SymbolTable *symtab) const override;
57};
58
|
53class StoreCond : public MemInst
| 59// load-reserved
60class LoadReserved : public RiscvMacroInst
|
54{
55 protected:
| 61{
62 protected:
|
56 using MemInst::MemInst;
| 63 using RiscvMacroInst::RiscvMacroInst;
|
57
58 std::string generateDisassembly(
59 Addr pc, const SymbolTable *symtab) const override;
60};
61
| 64
65 std::string generateDisassembly(
66 Addr pc, const SymbolTable *symtab) const override;
67};
68
|
| 69class LoadReservedMicro : public RiscvMicroInst
70{
71 protected:
72 Request::Flags memAccessFlags;
73 using RiscvMicroInst::RiscvMicroInst;
74
75 std::string generateDisassembly(
76 Addr pc, const SymbolTable *symtab) const override;
77};
78
79// store-cond
80class StoreCond : public RiscvMacroInst
81{
82 protected:
83 using RiscvMacroInst::RiscvMacroInst;
84
85 std::string generateDisassembly(
86 Addr pc, const SymbolTable *symtab) const override;
87};
88
89class StoreCondMicro : public RiscvMicroInst
90{
91 protected:
92 Request::Flags memAccessFlags;
93 using RiscvMicroInst::RiscvMicroInst;
94
95 std::string generateDisassembly(
96 Addr pc, const SymbolTable *symtab) const override;
97};
98
99// AMOs
|
62class AtomicMemOp : public RiscvMacroInst
63{
64 protected:
65 using RiscvMacroInst::RiscvMacroInst;
66
67 std::string generateDisassembly(
68 Addr pc, const SymbolTable *symtab) const override;
69};
70
71class AtomicMemOpMicro : public RiscvMicroInst
72{
73 protected:
74 Request::Flags memAccessFlags;
75 using RiscvMicroInst::RiscvMicroInst;
76
77 std::string generateDisassembly(
78 Addr pc, const SymbolTable *symtab) const override;
79};
80
| 100class AtomicMemOp : public RiscvMacroInst
101{
102 protected:
103 using RiscvMacroInst::RiscvMacroInst;
104
105 std::string generateDisassembly(
106 Addr pc, const SymbolTable *symtab) const override;
107};
108
109class AtomicMemOpMicro : public RiscvMicroInst
110{
111 protected:
112 Request::Flags memAccessFlags;
113 using RiscvMicroInst::RiscvMicroInst;
114
115 std::string generateDisassembly(
116 Addr pc, const SymbolTable *symtab) const override;
117};
118
|
| 119/**
120 * A generic atomic op class
121 */
122
123template<typename T>
124class AtomicGenericOp : public TypedAtomicOpFunctor<T>
125{
126 public:
127 AtomicGenericOp(T _a, std::function<void(T*,T)> _op)
128 : a(_a), op(_op) { }
129 AtomicOpFunctor* clone() { return new AtomicGenericOp<T>(*this); }
130 void execute(T *b) { op(b, a); }
131 private:
132 T a;
133 std::function<void(T*,T)> op;
134};
135
|
81}
82
83#endif // __ARCH_RISCV_INSTS_AMO_HH__
| 136}
137
138#endif // __ARCH_RISCV_INSTS_AMO_HH__
|