1/*
2 * Copyright (c) 2015 RISC-V Foundation
3 * Copyright (c) 2017 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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36
37#include "arch/riscv/insts/mem.hh"
38#include "arch/riscv/insts/static_inst.hh"
39#include "cpu/static_inst.hh"
40
41namespace RiscvISA
42{
43
44class LoadReserved : public MemInst
45{
46 protected:
47 using MemInst::MemInst;
48
49 std::string generateDisassembly(
50 Addr pc, const SymbolTable *symtab) const override;
51};
52
53class StoreCond : public MemInst
54{
55 protected:
56 using MemInst::MemInst;
57
58 std::string generateDisassembly(
59 Addr pc, const SymbolTable *symtab) const override;
60};
61
62class AtomicMemOp : public RiscvMacroInst
63{
64 protected:
65 using RiscvMacroInst::RiscvMacroInst;
66
67 std::string generateDisassembly(
68 Addr pc, const SymbolTable *symtab) const override;
69};
70
71class AtomicMemOpMicro : public RiscvMicroInst
72{
73 protected:
74 Request::Flags memAccessFlags;
75 using RiscvMicroInst::RiscvMicroInst;
76
77 std::string generateDisassembly(
78 Addr pc, const SymbolTable *symtab) const override;
79};
80
81}
82
83#endif // __ARCH_RISCV_INSTS_AMO_HH__