1/*
2 * Copyright (c) 2015 RISC-V Foundation
3 * Copyright (c) 2017 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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36
37#include "arch/riscv/insts/mem.hh"
38#include "arch/riscv/insts/static_inst.hh"
39#include "cpu/static_inst.hh"
40
41namespace RiscvISA
42{
43
44// memfence micro instruction
45class MemFenceMicro : public RiscvMicroInst
46{
47 public:
48 MemFenceMicro(ExtMachInst _machInst, OpClass __opClass)
49 : RiscvMicroInst("fence", _machInst, __opClass)
50 { }
51 protected:
52 using RiscvMicroInst::RiscvMicroInst;
53
54 Fault execute(ExecContext *, Trace::InstRecord *) const override;
55 std::string generateDisassembly(
56 Addr pc, const SymbolTable *symtab) const override;
57};
58
59// load-reserved
60class LoadReserved : public RiscvMacroInst
61{
62 protected:
63 using RiscvMacroInst::RiscvMacroInst;
64
65 std::string generateDisassembly(
66 Addr pc, const SymbolTable *symtab) const override;
67};
68
69class LoadReservedMicro : public RiscvMicroInst
70{
71 protected:
72 Request::Flags memAccessFlags;
73 using RiscvMicroInst::RiscvMicroInst;
74
75 std::string generateDisassembly(
76 Addr pc, const SymbolTable *symtab) const override;
77};
78
79// store-cond
80class StoreCond : public RiscvMacroInst
81{
82 protected:
83 using RiscvMacroInst::RiscvMacroInst;
84
85 std::string generateDisassembly(
86 Addr pc, const SymbolTable *symtab) const override;
87};
88
89class StoreCondMicro : public RiscvMicroInst
90{
91 protected:
92 Request::Flags memAccessFlags;
93 using RiscvMicroInst::RiscvMicroInst;
94
95 std::string generateDisassembly(
96 Addr pc, const SymbolTable *symtab) const override;
97};
98
99// AMOs
100class AtomicMemOp : public RiscvMacroInst
101{
102 protected:
103 using RiscvMacroInst::RiscvMacroInst;
104
105 std::string generateDisassembly(
106 Addr pc, const SymbolTable *symtab) const override;
107};
108
109class AtomicMemOpMicro : public RiscvMicroInst
110{
111 protected:
112 Request::Flags memAccessFlags;
113 using RiscvMicroInst::RiscvMicroInst;
114
115 std::string generateDisassembly(
116 Addr pc, const SymbolTable *symtab) const override;
117};
118
119/**
120 * A generic atomic op class
121 */
122
123template<typename T>
124class AtomicGenericOp : public TypedAtomicOpFunctor<T>
125{
126 public:
127 AtomicGenericOp(T _a, std::function<void(T*,T)> _op)
128 : a(_a), op(_op) { }
129 AtomicOpFunctor* clone() { return new AtomicGenericOp<T>(*this); }
130 void execute(T *b) { op(b, a); }
131 private:
132 T a;
133 std::function<void(T*,T)> op;
134};
135
136}
137
138#endif // __ARCH_RISCV_INSTS_AMO_HH__