amo.cc (12323:55d08b81ff39) | amo.cc (13653:079472978bca) |
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1/* 2 * Copyright (c) 2015 RISC-V Foundation 3 * Copyright (c) 2017 The University of Virginia 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 29 unchanged lines hidden (view full) --- 38#include "cpu/exec_context.hh" 39#include "cpu/static_inst.hh" 40 41using namespace std; 42 43namespace RiscvISA 44{ 45 | 1/* 2 * Copyright (c) 2015 RISC-V Foundation 3 * Copyright (c) 2017 The University of Virginia 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 29 unchanged lines hidden (view full) --- 38#include "cpu/exec_context.hh" 39#include "cpu/static_inst.hh" 40 41using namespace std; 42 43namespace RiscvISA 44{ 45 |
46// memfence micro instruction 47string MemFenceMicro::generateDisassembly(Addr pc, 48 const SymbolTable *symtab) const 49{ 50 stringstream ss; 51 ss << csprintf("0x%08x", machInst) << ' ' << mnemonic; 52 return ss.str(); 53} 54 55Fault MemFenceMicro::execute(ExecContext *xc, 56 Trace::InstRecord *traceData) const 57{ 58 return NoFault; 59} 60 61// load-reserved |
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46string LoadReserved::generateDisassembly(Addr pc, 47 const SymbolTable *symtab) const 48{ 49 stringstream ss; 50 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", (" 51 << registerName(_srcRegIdx[0]) << ')'; 52 return ss.str(); 53} 54 | 62string LoadReserved::generateDisassembly(Addr pc, 63 const SymbolTable *symtab) const 64{ 65 stringstream ss; 66 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", (" 67 << registerName(_srcRegIdx[0]) << ')'; 68 return ss.str(); 69} 70 |
71string LoadReservedMicro::generateDisassembly(Addr pc, 72 const SymbolTable *symtab) const 73{ 74 stringstream ss; 75 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", (" 76 << registerName(_srcRegIdx[0]) << ')'; 77 return ss.str(); 78} 79 80// store-conditional |
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55string StoreCond::generateDisassembly(Addr pc, 56 const SymbolTable *symtab) const 57{ 58 stringstream ss; 59 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " 60 << registerName(_srcRegIdx[1]) << ", (" 61 << registerName(_srcRegIdx[0]) << ')'; 62 return ss.str(); 63} 64 | 81string StoreCond::generateDisassembly(Addr pc, 82 const SymbolTable *symtab) const 83{ 84 stringstream ss; 85 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " 86 << registerName(_srcRegIdx[1]) << ", (" 87 << registerName(_srcRegIdx[0]) << ')'; 88 return ss.str(); 89} 90 |
91string StoreCondMicro::generateDisassembly(Addr pc, 92 const SymbolTable *symtab) const 93{ 94 stringstream ss; 95 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " 96 << registerName(_srcRegIdx[1]) << ", (" 97 << registerName(_srcRegIdx[0]) << ')'; 98 return ss.str(); 99} 100 101// AMOs |
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65string AtomicMemOp::generateDisassembly(Addr pc, 66 const SymbolTable *symtab) const 67{ 68 stringstream ss; 69 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " 70 << registerName(_srcRegIdx[1]) << ", (" 71 << registerName(_srcRegIdx[0]) << ')'; 72 return ss.str(); 73} 74 75string AtomicMemOpMicro::generateDisassembly(Addr pc, 76 const SymbolTable *symtab) const 77{ 78 stringstream ss; | 102string AtomicMemOp::generateDisassembly(Addr pc, 103 const SymbolTable *symtab) const 104{ 105 stringstream ss; 106 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " 107 << registerName(_srcRegIdx[1]) << ", (" 108 << registerName(_srcRegIdx[0]) << ')'; 109 return ss.str(); 110} 111 112string AtomicMemOpMicro::generateDisassembly(Addr pc, 113 const SymbolTable *symtab) const 114{ 115 stringstream ss; |
79 ss << csprintf("0x%08x", machInst) << ' ' << mnemonic; | 116 ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " 117 << registerName(_srcRegIdx[1]) << ", (" 118 << registerName(_srcRegIdx[0]) << ')'; |
80 return ss.str(); 81} 82 83} | 119 return ss.str(); 120} 121 122} |