faults.hh (13548:b76f99d052bb) faults.hh (13612:12ae022f3a30)
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

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39#include "arch/riscv/isa.hh"
40#include "arch/riscv/registers.hh"
41#include "cpu/thread_context.hh"
42#include "sim/faults.hh"
43
44namespace RiscvISA
45{
46
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

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39#include "arch/riscv/isa.hh"
40#include "arch/riscv/registers.hh"
41#include "cpu/thread_context.hh"
42#include "sim/faults.hh"
43
44namespace RiscvISA
45{
46
47enum FloatException : MiscReg {
47enum FloatException : uint64_t {
48 FloatInexact = 0x1,
49 FloatUnderflow = 0x2,
50 FloatOverflow = 0x4,
51 FloatDivZero = 0x8,
52 FloatInvalid = 0x10
53};
54
55/*
56 * In RISC-V, exception and interrupt codes share some values. They can be
57 * differentiated by an 'Interrupt' flag that is enabled for interrupt faults
58 * but not exceptions. The full fault cause can be computed by placing the
59 * exception (or interrupt) code in the least significant bits of the CAUSE
60 * CSR and then setting the highest bit of CAUSE with the 'Interrupt' flag.
61 * For more details on exception causes, see Chapter 3.1.20 of the RISC-V
62 * privileged specification v 1.10. Codes are enumerated in Table 3.6.
63 */
48 FloatInexact = 0x1,
49 FloatUnderflow = 0x2,
50 FloatOverflow = 0x4,
51 FloatDivZero = 0x8,
52 FloatInvalid = 0x10
53};
54
55/*
56 * In RISC-V, exception and interrupt codes share some values. They can be
57 * differentiated by an 'Interrupt' flag that is enabled for interrupt faults
58 * but not exceptions. The full fault cause can be computed by placing the
59 * exception (or interrupt) code in the least significant bits of the CAUSE
60 * CSR and then setting the highest bit of CAUSE with the 'Interrupt' flag.
61 * For more details on exception causes, see Chapter 3.1.20 of the RISC-V
62 * privileged specification v 1.10. Codes are enumerated in Table 3.6.
63 */
64enum ExceptionCode : MiscReg {
64enum ExceptionCode : uint64_t {
65 INST_ADDR_MISALIGNED = 0,
66 INST_ACCESS = 1,
67 INST_ILLEGAL = 2,
68 BREAKPOINT = 3,
69 LOAD_ADDR_MISALIGNED = 4,
70 LOAD_ACCESS = 5,
71 STORE_ADDR_MISALIGNED = 6,
72 AMO_ADDR_MISALIGNED = 6,

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101
102 RiscvFault(FaultName n, bool i, ExceptionCode c)
103 : _name(n), _interrupt(i), _code(c)
104 {}
105
106 FaultName name() const override { return _name; }
107 bool isInterrupt() const { return _interrupt; }
108 ExceptionCode exception() const { return _code; }
65 INST_ADDR_MISALIGNED = 0,
66 INST_ACCESS = 1,
67 INST_ILLEGAL = 2,
68 BREAKPOINT = 3,
69 LOAD_ADDR_MISALIGNED = 4,
70 LOAD_ACCESS = 5,
71 STORE_ADDR_MISALIGNED = 6,
72 AMO_ADDR_MISALIGNED = 6,

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101
102 RiscvFault(FaultName n, bool i, ExceptionCode c)
103 : _name(n), _interrupt(i), _code(c)
104 {}
105
106 FaultName name() const override { return _name; }
107 bool isInterrupt() const { return _interrupt; }
108 ExceptionCode exception() const { return _code; }
109 virtual MiscReg trap_value() const { return 0; }
109 virtual RegVal trap_value() const { return 0; }
110
111 virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst);
112 void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
113};
114
115class Reset : public FaultBase
116{
117 private:

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137 protected:
138 const ExtMachInst _inst;
139
140 public:
141 InstFault(FaultName n, const ExtMachInst inst)
142 : RiscvFault(n, false, INST_ILLEGAL), _inst(inst)
143 {}
144
110
111 virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst);
112 void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
113};
114
115class Reset : public FaultBase
116{
117 private:

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137 protected:
138 const ExtMachInst _inst;
139
140 public:
141 InstFault(FaultName n, const ExtMachInst inst)
142 : RiscvFault(n, false, INST_ILLEGAL), _inst(inst)
143 {}
144
145 MiscReg trap_value() const override { return _inst; }
145 RegVal trap_value() const override { return _inst; }
146};
147
148class UnknownInstFault : public InstFault
149{
150 public:
151 UnknownInstFault(const ExtMachInst inst)
152 : InstFault("Unknown instruction", inst)
153 {}

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201 private:
202 const Addr _addr;
203
204 public:
205 AddressFault(const Addr addr, ExceptionCode code)
206 : RiscvFault("Address", false, code), _addr(addr)
207 {}
208
146};
147
148class UnknownInstFault : public InstFault
149{
150 public:
151 UnknownInstFault(const ExtMachInst inst)
152 : InstFault("Unknown instruction", inst)
153 {}

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201 private:
202 const Addr _addr;
203
204 public:
205 AddressFault(const Addr addr, ExceptionCode code)
206 : RiscvFault("Address", false, code), _addr(addr)
207 {}
208
209 MiscReg trap_value() const override { return _addr; }
209 RegVal trap_value() const override { return _addr; }
210};
211
212class BreakpointFault : public RiscvFault
213{
214 private:
215 const PCState pcState;
216
217 public:
218 BreakpointFault(const PCState &pc)
219 : RiscvFault("Breakpoint", false, BREAKPOINT), pcState(pc)
220 {}
221
210};
211
212class BreakpointFault : public RiscvFault
213{
214 private:
215 const PCState pcState;
216
217 public:
218 BreakpointFault(const PCState &pc)
219 : RiscvFault("Breakpoint", false, BREAKPOINT), pcState(pc)
220 {}
221
222 MiscReg trap_value() const override { return pcState.pc(); }
222 RegVal trap_value() const override { return pcState.pc(); }
223 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
224};
225
226class SyscallFault : public RiscvFault
227{
228 public:
229 SyscallFault(PrivilegeMode prv)
230 : RiscvFault("System call", false, ECALL_USER)

--- 23 unchanged lines hidden --- 		223 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
224};
225
226class SyscallFault : public RiscvFault
227{
228 public:
229 SyscallFault(PrivilegeMode prv)
230 : RiscvFault("System call", false, ECALL_USER)

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