faults.hh (13547:2aff46b9bbc5) faults.hh (13548:b76f99d052bb)
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

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29 *
30 * Authors: Alec Roelke
31 * Robert Scheffel
32 */
33
34#ifndef __ARCH_RISCV_FAULTS_HH__
35#define __ARCH_RISCV_FAULTS_HH__
36
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

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29 *
30 * Authors: Alec Roelke
31 * Robert Scheffel
32 */
33
34#ifndef __ARCH_RISCV_FAULTS_HH__
35#define __ARCH_RISCV_FAULTS_HH__
36
37#include <map>
38#include <string>
39
40#include "arch/riscv/isa.hh"
41#include "arch/riscv/registers.hh"
42#include "cpu/thread_context.hh"
43#include "sim/faults.hh"
44
45namespace RiscvISA
46{
47
48enum FloatException : MiscReg {
49 FloatInexact = 0x1,
50 FloatUnderflow = 0x2,
51 FloatOverflow = 0x4,
52 FloatDivZero = 0x8,
53 FloatInvalid = 0x10
54};
55
37#include <string>
38
39#include "arch/riscv/isa.hh"
40#include "arch/riscv/registers.hh"
41#include "cpu/thread_context.hh"
42#include "sim/faults.hh"
43
44namespace RiscvISA
45{
46
47enum FloatException : MiscReg {
48 FloatInexact = 0x1,
49 FloatUnderflow = 0x2,
50 FloatOverflow = 0x4,
51 FloatDivZero = 0x8,
52 FloatInvalid = 0x10
53};
54
55/*
56 * In RISC-V, exception and interrupt codes share some values. They can be
57 * differentiated by an 'Interrupt' flag that is enabled for interrupt faults
58 * but not exceptions. The full fault cause can be computed by placing the
59 * exception (or interrupt) code in the least significant bits of the CAUSE
60 * CSR and then setting the highest bit of CAUSE with the 'Interrupt' flag.
61 * For more details on exception causes, see Chapter 3.1.20 of the RISC-V
62 * privileged specification v 1.10. Codes are enumerated in Table 3.6.
63 */
56enum ExceptionCode : MiscReg {
57 INST_ADDR_MISALIGNED = 0,
58 INST_ACCESS = 1,
59 INST_ILLEGAL = 2,
60 BREAKPOINT = 3,
61 LOAD_ADDR_MISALIGNED = 4,
62 LOAD_ACCESS = 5,
63 STORE_ADDR_MISALIGNED = 6,
64 AMO_ADDR_MISALIGNED = 6,
65 STORE_ACCESS = 7,
66 AMO_ACCESS = 7,
67 ECALL_USER = 8,
68 ECALL_SUPER = 9,
69 ECALL_MACHINE = 11,
70 INST_PAGE = 12,
71 LOAD_PAGE = 13,
72 STORE_PAGE = 15,
64enum ExceptionCode : MiscReg {
65 INST_ADDR_MISALIGNED = 0,
66 INST_ACCESS = 1,
67 INST_ILLEGAL = 2,
68 BREAKPOINT = 3,
69 LOAD_ADDR_MISALIGNED = 4,
70 LOAD_ACCESS = 5,
71 STORE_ADDR_MISALIGNED = 6,
72 AMO_ADDR_MISALIGNED = 6,
73 STORE_ACCESS = 7,
74 AMO_ACCESS = 7,
75 ECALL_USER = 8,
76 ECALL_SUPER = 9,
77 ECALL_MACHINE = 11,
78 INST_PAGE = 12,
79 LOAD_PAGE = 13,
80 STORE_PAGE = 15,
73 AMO_PAGE = 15
81 AMO_PAGE = 15,
82
83 INT_SOFTWARE_USER = 0,
84 INT_SOFTWARE_SUPER = 1,
85 INT_SOFTWARE_MACHINE = 3,
86 INT_TIMER_USER = 4,
87 INT_TIMER_SUPER = 5,
88 INT_TIMER_MACHINE = 7,
89 INT_EXT_USER = 8,
90 INT_EXT_SUPER = 9,
91 INT_EXT_MACHINE = 11,
92 NumInterruptTypes
74};
75
76class RiscvFault : public FaultBase
77{
78 protected:
79 const FaultName _name;
80 const bool _interrupt;
81 ExceptionCode _code;

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101 public:
102 Reset() : _name("reset") {}
103 FaultName name() const override { return _name; }
104
105 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
106 StaticInst::nullStaticInstPtr) override;
107};
108
93};
94
95class RiscvFault : public FaultBase
96{
97 protected:
98 const FaultName _name;
99 const bool _interrupt;
100 ExceptionCode _code;

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120 public:
121 Reset() : _name("reset") {}
122 FaultName name() const override { return _name; }
123
124 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
125 StaticInst::nullStaticInstPtr) override;
126};
127
128class InterruptFault : public RiscvFault
129{
130 public:
131 InterruptFault(ExceptionCode c) : RiscvFault("interrupt", true, c) {}
132 InterruptFault(int c) : InterruptFault(static_cast<ExceptionCode>(c)) {}
133};
134
109class InstFault : public RiscvFault
110{
111 protected:
112 const ExtMachInst _inst;
113
114 public:
115 InstFault(FaultName n, const ExtMachInst inst)
116 : RiscvFault(n, false, INST_ILLEGAL), _inst(inst)

--- 111 unchanged lines hidden --- 		135class InstFault : public RiscvFault
136{
137 protected:
138 const ExtMachInst _inst;
139
140 public:
141 InstFault(FaultName n, const ExtMachInst inst)
142 : RiscvFault(n, false, INST_ILLEGAL), _inst(inst)

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