faults.hh (12849:7f43ad13ebf0) | faults.hh (12850:7036cad54910) |
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1/* 2 * Copyright (c) 2016 RISC-V Foundation 3 * Copyright (c) 2016 The University of Virginia 4 * Copyright (c) 2018 TU Dresden 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are --- 20 unchanged lines hidden (view full) --- 29 * 30 * Authors: Alec Roelke 31 * Robert Scheffel 32 */ 33 34#ifndef __ARCH_RISCV_FAULTS_HH__ 35#define __ARCH_RISCV_FAULTS_HH__ 36 | 1/* 2 * Copyright (c) 2016 RISC-V Foundation 3 * Copyright (c) 2016 The University of Virginia 4 * Copyright (c) 2018 TU Dresden 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are --- 20 unchanged lines hidden (view full) --- 29 * 30 * Authors: Alec Roelke 31 * Robert Scheffel 32 */ 33 34#ifndef __ARCH_RISCV_FAULTS_HH__ 35#define __ARCH_RISCV_FAULTS_HH__ 36 |
37#include <map> |
|
37#include <string> 38 | 38#include <string> 39 |
40#include "arch/riscv/isa.hh" |
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39#include "arch/riscv/registers.hh" 40#include "cpu/thread_context.hh" 41#include "sim/faults.hh" 42 43namespace RiscvISA 44{ 45 46enum FloatException : MiscReg { --- 19 unchanged lines hidden (view full) --- 66 ECALL_SUPER = 9, 67 ECALL_MACHINE = 11, 68 INST_PAGE = 12, 69 LOAD_PAGE = 13, 70 STORE_PAGE = 15, 71 AMO_PAGE = 15 72}; 73 | 41#include "arch/riscv/registers.hh" 42#include "cpu/thread_context.hh" 43#include "sim/faults.hh" 44 45namespace RiscvISA 46{ 47 48enum FloatException : MiscReg { --- 19 unchanged lines hidden (view full) --- 68 ECALL_SUPER = 9, 69 ECALL_MACHINE = 11, 70 INST_PAGE = 12, 71 LOAD_PAGE = 13, 72 STORE_PAGE = 15, 73 AMO_PAGE = 15 74}; 75 |
74/** 75 * These fields are specified in the RISC-V Instruction Set Manual, Volume II, 76 * v1.10, accessible at www.riscv.org. in Figure 3.7. The main register that 77 * uses these fields is the MSTATUS register, which is shadowed by two others 78 * accessible at lower privilege levels (SSTATUS and USTATUS) that can't see 79 * the fields for higher privileges. 80 */ 81BitUnion64(STATUS) 82 Bitfield<63> sd; 83 Bitfield<35, 34> sxl; 84 Bitfield<33, 32> uxl; 85 Bitfield<22> tsr; 86 Bitfield<21> tw; 87 Bitfield<20> tvm; 88 Bitfield<19> mxr; 89 Bitfield<18> sum; 90 Bitfield<17> mprv; 91 Bitfield<16, 15> xs; 92 Bitfield<14, 13> fs; 93 Bitfield<12, 11> mpp; 94 Bitfield<8> spp; 95 Bitfield<7> mpie; 96 Bitfield<5> spie; 97 Bitfield<4> upie; 98 Bitfield<3> mie; 99 Bitfield<1> sie; 100 Bitfield<0> uie; 101EndBitUnion(STATUS) 102 103/** 104 * These fields are specified in the RISC-V Instruction Set Manual, Volume II, 105 * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the MIP 106 * and MIE registers have the same fields, so accesses to either should use 107 * this bit union. 108 */ 109BitUnion64(INTERRUPT) 110 Bitfield<11> mei; 111 Bitfield<9> sei; 112 Bitfield<8> uei; 113 Bitfield<7> mti; 114 Bitfield<5> sti; 115 Bitfield<4> uti; 116 Bitfield<3> msi; 117 Bitfield<1> ssi; 118 Bitfield<0> usi; 119EndBitUnion(INTERRUPT) 120 | |
121class RiscvFault : public FaultBase 122{ 123 protected: 124 const FaultName _name; | 76class RiscvFault : public FaultBase 77{ 78 protected: 79 const FaultName _name; |
125 bool _interrupt; 126 const ExceptionCode _code; | 80 const bool _interrupt; 81 ExceptionCode _code; |
127 128 RiscvFault(FaultName n, bool i, ExceptionCode c) 129 : _name(n), _interrupt(i), _code(c) 130 {} 131 132 FaultName name() const override { return _name; } 133 bool isInterrupt() const { return _interrupt; } 134 ExceptionCode exception() const { return _code; } --- 114 unchanged lines hidden (view full) --- 249 250 MiscReg trap_value() const override { return pcState.pc(); } 251 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 252}; 253 254class SyscallFault : public RiscvFault 255{ 256 public: | 82 83 RiscvFault(FaultName n, bool i, ExceptionCode c) 84 : _name(n), _interrupt(i), _code(c) 85 {} 86 87 FaultName name() const override { return _name; } 88 bool isInterrupt() const { return _interrupt; } 89 ExceptionCode exception() const { return _code; } --- 114 unchanged lines hidden (view full) --- 204 205 MiscReg trap_value() const override { return pcState.pc(); } 206 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 207}; 208 209class SyscallFault : public RiscvFault 210{ 211 public: |
257 // TODO: replace ECALL_USER with the appropriate privilege level of the 258 // caller 259 SyscallFault() : RiscvFault("System call", false, ECALL_USER) {} | 212 SyscallFault(PrivilegeMode prv) 213 : RiscvFault("System call", false, ECALL_USER) 214 { 215 switch (prv) { 216 case PRV_U: 217 _code = ECALL_USER; 218 break; 219 case PRV_S: 220 _code = ECALL_SUPER; 221 break; 222 case PRV_M: 223 _code = ECALL_MACHINE; 224 break; 225 default: 226 panic("Unknown privilege mode %d.", prv); 227 break; 228 } 229 } 230 |
260 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 261}; 262 263} // namespace RiscvISA 264 265#endif // __ARCH_RISCV_FAULTS_HH__ | 231 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 232}; 233 234} // namespace RiscvISA 235 236#endif // __ARCH_RISCV_FAULTS_HH__ |