faults.hh (12808:f275fd1244ce) faults.hh (12848:67652b15de3b)
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

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31 * Robert Scheffel
32 */
33
34#ifndef __ARCH_RISCV_FAULTS_HH__
35#define __ARCH_RISCV_FAULTS_HH__
36
37#include <string>
38
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

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31 * Robert Scheffel
32 */
33
34#ifndef __ARCH_RISCV_FAULTS_HH__
35#define __ARCH_RISCV_FAULTS_HH__
36
37#include <string>
38
39#include "arch/riscv/registers.hh"
39#include "cpu/thread_context.hh"
40#include "sim/faults.hh"
41
42namespace RiscvISA
43{
44
40#include "cpu/thread_context.hh"
41#include "sim/faults.hh"
42
43namespace RiscvISA
44{
45
45const uint32_t FloatInexact = 1 << 0;
46const uint32_t FloatUnderflow = 1 << 1;
47const uint32_t FloatOverflow = 1 << 2;
48const uint32_t FloatDivZero = 1 << 3;
49const uint32_t FloatInvalid = 1 << 4;
46enum FloatException : MiscReg {
47 FloatInexact = 0x1,
48 FloatUnderflow = 0x2,
49 FloatOverflow = 0x4,
50 FloatDivZero = 0x8,
51 FloatInvalid = 0x10
52};
50
53
51enum ExceptionCode {
54enum ExceptionCode : MiscReg {
52 INST_ADDR_MISALIGNED = 0,
53 INST_ACCESS = 1,
54 INST_ILLEGAL = 2,
55 BREAKPOINT = 3,
56 LOAD_ADDR_MISALIGNED = 4,
57 LOAD_ACCESS = 5,
58 STORE_ADDR_MISALIGNED = 6,
59 AMO_ADDR_MISALIGNED = 6,
60 STORE_ACCESS = 7,
61 AMO_ACCESS = 7,
62 ECALL_USER = 8,
63 ECALL_SUPER = 9,
55 INST_ADDR_MISALIGNED = 0,
56 INST_ACCESS = 1,
57 INST_ILLEGAL = 2,
58 BREAKPOINT = 3,
59 LOAD_ADDR_MISALIGNED = 4,
60 LOAD_ACCESS = 5,
61 STORE_ADDR_MISALIGNED = 6,
62 AMO_ADDR_MISALIGNED = 6,
63 STORE_ACCESS = 7,
64 AMO_ACCESS = 7,
65 ECALL_USER = 8,
66 ECALL_SUPER = 9,
64 ECALL_HYPER = 10,
65 ECALL_MACH = 11
67 ECALL_MACHINE = 11,
68 INST_PAGE = 12,
69 LOAD_PAGE = 13,
70 STORE_PAGE = 15,
71 AMO_PAGE = 15
66};
67
72};
73
68enum InterruptCode {
69 SOFTWARE,
70 TIMER
71};
74/**
75 * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
76 * v1.10, accessible at www.riscv.org. in Figure 3.7. The main register that
77 * uses these fields is the MSTATUS register, which is shadowed by two others
78 * accessible at lower privilege levels (SSTATUS and USTATUS) that can't see
79 * the fields for higher privileges.
80 */
81BitUnion64(STATUS)
82 Bitfield<63> sd;
83 Bitfield<35, 34> sxl;
84 Bitfield<33, 32> uxl;
85 Bitfield<22> tsr;
86 Bitfield<21> tw;
87 Bitfield<20> tvm;
88 Bitfield<19> mxr;
89 Bitfield<18> sum;
90 Bitfield<17> mprv;
91 Bitfield<16, 15> xs;
92 Bitfield<14, 13> fs;
93 Bitfield<12, 11> mpp;
94 Bitfield<8> spp;
95 Bitfield<7> mpie;
96 Bitfield<5> spie;
97 Bitfield<4> upie;
98 Bitfield<3> mie;
99 Bitfield<1> sie;
100 Bitfield<0> uie;
101EndBitUnion(STATUS)
72
102
103/**
104 * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
105 * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the MIP
106 * and MIE registers have the same fields, so accesses to either should use
107 * this bit union.
108 */
109BitUnion64(INTERRUPT)
110 Bitfield<11> mei;
111 Bitfield<9> sei;
112 Bitfield<8> uei;
113 Bitfield<7> mti;
114 Bitfield<5> sti;
115 Bitfield<4> uti;
116 Bitfield<3> msi;
117 Bitfield<1> ssi;
118 Bitfield<0> usi;
119EndBitUnion(INTERRUPT)
120
73class RiscvFault : public FaultBase
74{
75 protected:
76 const FaultName _name;
121class RiscvFault : public FaultBase
122{
123 protected:
124 const FaultName _name;
125 bool _interrupt;
77 const ExceptionCode _code;
126 const ExceptionCode _code;
78 const InterruptCode _int;
79
127
80 RiscvFault(FaultName n, ExceptionCode c, InterruptCode i)
81 : _name(n), _code(c), _int(i)
128 RiscvFault(FaultName n, bool i, ExceptionCode c)
129 : _name(n), _interrupt(i), _code(c)
82 {}
83
130 {}
131
84 FaultName
85 name() const
86 {
87 return _name;
88 }
132 FaultName name() const { return _name; }
133 bool isInterrupt() const { return _interrupt; }
134 ExceptionCode exception() const { return _code; }
89
135
90 ExceptionCode
91 exception() const
92 {
93 return _code;
94 }
95
96 InterruptCode
97 interrupt() const
98 {
99 return _int;
100 }
101
102 virtual void
103 invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
104
105 void
106 invoke(ThreadContext *tc, const StaticInstPtr &inst);
136 virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst);
137 void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
107};
108
109class Reset : public FaultBase
110{
111
112 public:
113 Reset()
114 : _name("reset")

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126
127 private:
128 const FaultName _name;
129};
130
131class UnknownInstFault : public RiscvFault
132{
133 public:
138};
139
140class Reset : public FaultBase
141{
142
143 public:
144 Reset()
145 : _name("reset")

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157
158 private:
159 const FaultName _name;
160};
161
162class UnknownInstFault : public RiscvFault
163{
164 public:
134 UnknownInstFault() : RiscvFault("Unknown instruction", INST_ILLEGAL,
135 SOFTWARE)
165 UnknownInstFault() : RiscvFault("Unknown instruction", false, INST_ILLEGAL)
136 {}
137
166 {}
167
138 void
139 invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
168 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
140};
141
142class IllegalInstFault : public RiscvFault
143{
144 private:
145 const std::string reason;
169};
170
171class IllegalInstFault : public RiscvFault
172{
173 private:
174 const std::string reason;
175
146 public:
147 IllegalInstFault(std::string r)
176 public:
177 IllegalInstFault(std::string r)
148 : RiscvFault("Illegal instruction", INST_ILLEGAL, SOFTWARE),
149 reason(r)
178 : RiscvFault("Illegal instruction", false, INST_ILLEGAL)
150 {}
151
179 {}
180
152 void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
181 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
153};
154
155class UnimplementedFault : public RiscvFault
156{
157 private:
158 const std::string instName;
182};
183
184class UnimplementedFault : public RiscvFault
185{
186 private:
187 const std::string instName;
188
159 public:
160 UnimplementedFault(std::string name)
189 public:
190 UnimplementedFault(std::string name)
161 : RiscvFault("Unimplemented instruction", INST_ILLEGAL, SOFTWARE),
162 instName(name)
191 : RiscvFault("Unimplemented instruction", false, INST_ILLEGAL),
192 instName(name)
163 {}
164
193 {}
194
165 void
166 invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
195 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
167};
168
169class IllegalFrmFault: public RiscvFault
170{
171 private:
172 const uint8_t frm;
196};
197
198class IllegalFrmFault: public RiscvFault
199{
200 private:
201 const uint8_t frm;
202
173 public:
174 IllegalFrmFault(uint8_t r)
203 public:
204 IllegalFrmFault(uint8_t r)
175 : RiscvFault("Illegal floating-point rounding mode", INST_ILLEGAL,
176 SOFTWARE),
177 frm(r)
205 : RiscvFault("Illegal floating-point rounding mode", false,
206 INST_ILLEGAL),
207 frm(r)
178 {}
179
208 {}
209
180 void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
210 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
181};
182
183class BreakpointFault : public RiscvFault
184{
185 public:
211};
212
213class BreakpointFault : public RiscvFault
214{
215 public:
186 BreakpointFault() : RiscvFault("Breakpoint", BREAKPOINT, SOFTWARE)
187 {}
188
189 void
190 invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
216 BreakpointFault() : RiscvFault("Breakpoint", false, BREAKPOINT) {}
217 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
191};
192
193class SyscallFault : public RiscvFault
194{
195 public:
196 // TODO: replace ECALL_USER with the appropriate privilege level of the
197 // caller
218};
219
220class SyscallFault : public RiscvFault
221{
222 public:
223 // TODO: replace ECALL_USER with the appropriate privilege level of the
224 // caller
198 SyscallFault() : RiscvFault("System call", ECALL_USER, SOFTWARE)
199 {}
200
201 void
202 invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
225 SyscallFault() : RiscvFault("System call", false, ECALL_USER) {}
226 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
203};
204
205} // namespace RiscvISA
206
207#endif // __ARCH_RISCV_FAULTS_HH__
227};
228
229} // namespace RiscvISA
230
231#endif // __ARCH_RISCV_FAULTS_HH__