1/* 2 * Copyright (c) 2016 RISC-V Foundation 3 * Copyright (c) 2016 The University of Virginia 4 * Copyright (c) 2018 TU Dresden 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are --- 20 unchanged lines hidden (view full) --- 29 * 30 * Authors: Alec Roelke 31 * Robert Scheffel 32 */ 33 34#ifndef __ARCH_RISCV_FAULTS_HH__ 35#define __ARCH_RISCV_FAULTS_HH__ 36 |
37#include <map> |
38#include <string> 39 |
40#include "arch/riscv/isa.hh" |
41#include "arch/riscv/registers.hh" 42#include "cpu/thread_context.hh" 43#include "sim/faults.hh" 44 45namespace RiscvISA 46{ 47 48enum FloatException : MiscReg { --- 19 unchanged lines hidden (view full) --- 68 ECALL_SUPER = 9, 69 ECALL_MACHINE = 11, 70 INST_PAGE = 12, 71 LOAD_PAGE = 13, 72 STORE_PAGE = 15, 73 AMO_PAGE = 15 74}; 75 |
76class RiscvFault : public FaultBase 77{ 78 protected: 79 const FaultName _name; |
80 const bool _interrupt; 81 ExceptionCode _code; |
82 83 RiscvFault(FaultName n, bool i, ExceptionCode c) 84 : _name(n), _interrupt(i), _code(c) 85 {} 86 87 FaultName name() const override { return _name; } 88 bool isInterrupt() const { return _interrupt; } 89 ExceptionCode exception() const { return _code; } --- 114 unchanged lines hidden (view full) --- 204 205 MiscReg trap_value() const override { return pcState.pc(); } 206 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 207}; 208 209class SyscallFault : public RiscvFault 210{ 211 public: |
212 SyscallFault(PrivilegeMode prv) 213 : RiscvFault("System call", false, ECALL_USER) 214 { 215 switch (prv) { 216 case PRV_U: 217 _code = ECALL_USER; 218 break; 219 case PRV_S: 220 _code = ECALL_SUPER; 221 break; 222 case PRV_M: 223 _code = ECALL_MACHINE; 224 break; 225 default: 226 panic("Unknown privilege mode %d.", prv); 227 break; 228 } 229 } 230 |
231 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 232}; 233 234} // namespace RiscvISA 235 236#endif // __ARCH_RISCV_FAULTS_HH__ |