1/* 2 * Copyright (c) 2016 RISC-V Foundation 3 * Copyright (c) 2016 The University of Virginia 4 * Copyright (c) 2018 TU Dresden 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are --- 115 unchanged lines hidden (view full) --- 124 const FaultName _name; 125 bool _interrupt; 126 const ExceptionCode _code; 127 128 RiscvFault(FaultName n, bool i, ExceptionCode c) 129 : _name(n), _interrupt(i), _code(c) 130 {} 131 |
132 FaultName name() const override { return _name; } |
133 bool isInterrupt() const { return _interrupt; } 134 ExceptionCode exception() const { return _code; } |
135 virtual MiscReg trap_value() const { return 0; } |
136 137 virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst); 138 void invoke(ThreadContext *tc, const StaticInstPtr &inst) override; 139}; 140 141class Reset : public FaultBase 142{ 143 --- 11 unchanged lines hidden (view full) --- 155 void 156 invoke(ThreadContext *tc, const StaticInstPtr &inst = 157 StaticInst::nullStaticInstPtr) override; 158 159 private: 160 const FaultName _name; 161}; 162 |
163class InstFault : public RiscvFault |
164{ |
165 protected: 166 const ExtMachInst _inst; 167 |
168 public: |
169 InstFault(FaultName n, const ExtMachInst inst) 170 : RiscvFault(n, false, INST_ILLEGAL), _inst(inst) |
171 {} 172 |
173 MiscReg trap_value() const override { return _inst; } 174}; 175 176class UnknownInstFault : public InstFault 177{ 178 public: 179 UnknownInstFault(const ExtMachInst inst) 180 : InstFault("Unknown instruction", inst) 181 {} 182 |
183 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 184}; 185 |
186class IllegalInstFault : public InstFault |
187{ 188 private: 189 const std::string reason; 190 191 public: |
192 IllegalInstFault(std::string r, const ExtMachInst inst) 193 : InstFault("Illegal instruction", inst) |
194 {} 195 196 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 197}; 198 |
199class UnimplementedFault : public InstFault |
200{ 201 private: 202 const std::string instName; 203 204 public: |
205 UnimplementedFault(std::string name, const ExtMachInst inst) 206 : InstFault("Unimplemented instruction", inst), |
207 instName(name) 208 {} 209 210 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 211}; 212 |
213class IllegalFrmFault: public InstFault |
214{ 215 private: 216 const uint8_t frm; 217 218 public: |
219 IllegalFrmFault(uint8_t r, const ExtMachInst inst) 220 : InstFault("Illegal floating-point rounding mode", inst), |
221 frm(r) 222 {} 223 224 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 225}; 226 |
227class AddressFault : public RiscvFault 228{ 229 private: 230 const Addr _addr; 231 232 public: 233 AddressFault(const Addr addr, ExceptionCode code) 234 : RiscvFault("Address", false, code), _addr(addr) 235 {} 236 237 MiscReg trap_value() const override { return _addr; } 238}; 239 |
240class BreakpointFault : public RiscvFault 241{ |
242 private: 243 const PCState pcState; 244 |
245 public: |
246 BreakpointFault(const PCState &pc) 247 : RiscvFault("Breakpoint", false, BREAKPOINT), pcState(pc) 248 {} 249 250 MiscReg trap_value() const override { return pcState.pc(); } |
251 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 252}; 253 254class SyscallFault : public RiscvFault 255{ 256 public: 257 // TODO: replace ECALL_USER with the appropriate privilege level of the 258 // caller 259 SyscallFault() : RiscvFault("System call", false, ECALL_USER) {} 260 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 261}; 262 263} // namespace RiscvISA 264 265#endif // __ARCH_RISCV_FAULTS_HH__ |