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< #include <map>
55a55,63
> /*
> * In RISC-V, exception and interrupt codes share some values. They can be
> * differentiated by an 'Interrupt' flag that is enabled for interrupt faults
> * but not exceptions. The full fault cause can be computed by placing the
> * exception (or interrupt) code in the least significant bits of the CAUSE
> * CSR and then setting the highest bit of CAUSE with the 'Interrupt' flag.
> * For more details on exception causes, see Chapter 3.1.20 of the RISC-V
> * privileged specification v 1.10. Codes are enumerated in Table 3.6.
> */
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< AMO_PAGE = 15
---
> AMO_PAGE = 15,
>
> INT_SOFTWARE_USER = 0,
> INT_SOFTWARE_SUPER = 1,
> INT_SOFTWARE_MACHINE = 3,
> INT_TIMER_USER = 4,
> INT_TIMER_SUPER = 5,
> INT_TIMER_MACHINE = 7,
> INT_EXT_USER = 8,
> INT_EXT_SUPER = 9,
> INT_EXT_MACHINE = 11,
> NumInterruptTypes
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> class InterruptFault : public RiscvFault
> {
> public:
> InterruptFault(ExceptionCode c) : RiscvFault("interrupt", true, c) {}
> InterruptFault(int c) : InterruptFault(static_cast<ExceptionCode>(c)) {}
> };
>