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> #include <map>
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> #include "arch/riscv/isa.hh"
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< /**
< * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
< * v1.10, accessible at www.riscv.org. in Figure 3.7. The main register that
< * uses these fields is the MSTATUS register, which is shadowed by two others
< * accessible at lower privilege levels (SSTATUS and USTATUS) that can't see
< * the fields for higher privileges.
< */
< BitUnion64(STATUS)
< Bitfield<63> sd;
< Bitfield<35, 34> sxl;
< Bitfield<33, 32> uxl;
< Bitfield<22> tsr;
< Bitfield<21> tw;
< Bitfield<20> tvm;
< Bitfield<19> mxr;
< Bitfield<18> sum;
< Bitfield<17> mprv;
< Bitfield<16, 15> xs;
< Bitfield<14, 13> fs;
< Bitfield<12, 11> mpp;
< Bitfield<8> spp;
< Bitfield<7> mpie;
< Bitfield<5> spie;
< Bitfield<4> upie;
< Bitfield<3> mie;
< Bitfield<1> sie;
< Bitfield<0> uie;
< EndBitUnion(STATUS)
<
< /**
< * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
< * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the MIP
< * and MIE registers have the same fields, so accesses to either should use
< * this bit union.
< */
< BitUnion64(INTERRUPT)
< Bitfield<11> mei;
< Bitfield<9> sei;
< Bitfield<8> uei;
< Bitfield<7> mti;
< Bitfield<5> sti;
< Bitfield<4> uti;
< Bitfield<3> msi;
< Bitfield<1> ssi;
< Bitfield<0> usi;
< EndBitUnion(INTERRUPT)
<
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< bool _interrupt;
< const ExceptionCode _code;
---
> const bool _interrupt;
> ExceptionCode _code;
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< // TODO: replace ECALL_USER with the appropriate privilege level of the
< // caller
< SyscallFault() : RiscvFault("System call", false, ECALL_USER) {}
---
> SyscallFault(PrivilegeMode prv)
> : RiscvFault("System call", false, ECALL_USER)
> {
> switch (prv) {
> case PRV_U:
> _code = ECALL_USER;
> break;
> case PRV_S:
> _code = ECALL_SUPER;
> break;
> case PRV_M:
> _code = ECALL_MACHINE;
> break;
> default:
> panic("Unknown privilege mode %d.", prv);
> break;
> }
> }
>