1/* 2 * Copyright (c) 2016 RISC-V Foundation 3 * Copyright (c) 2016 The University of Virginia 4 * Copyright (c) 2018 TU Dresden 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer; 11 * redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution; 14 * neither the name of the copyright holders nor the names of its 15 * contributors may be used to endorse or promote products derived from 16 * this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 * Authors: Alec Roelke 31 * Robert Scheffel 32 */ 33 34#ifndef __ARCH_RISCV_FAULTS_HH__ 35#define __ARCH_RISCV_FAULTS_HH__ 36
| 1/* 2 * Copyright (c) 2016 RISC-V Foundation 3 * Copyright (c) 2016 The University of Virginia 4 * Copyright (c) 2018 TU Dresden 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer; 11 * redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution; 14 * neither the name of the copyright holders nor the names of its 15 * contributors may be used to endorse or promote products derived from 16 * this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 * Authors: Alec Roelke 31 * Robert Scheffel 32 */ 33 34#ifndef __ARCH_RISCV_FAULTS_HH__ 35#define __ARCH_RISCV_FAULTS_HH__ 36
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37#include <map>
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38#include <string> 39 40#include "arch/riscv/isa.hh" 41#include "arch/riscv/registers.hh" 42#include "cpu/thread_context.hh" 43#include "sim/faults.hh" 44 45namespace RiscvISA 46{ 47 48enum FloatException : MiscReg { 49 FloatInexact = 0x1, 50 FloatUnderflow = 0x2, 51 FloatOverflow = 0x4, 52 FloatDivZero = 0x8, 53 FloatInvalid = 0x10 54}; 55
| 37#include <string> 38 39#include "arch/riscv/isa.hh" 40#include "arch/riscv/registers.hh" 41#include "cpu/thread_context.hh" 42#include "sim/faults.hh" 43 44namespace RiscvISA 45{ 46 47enum FloatException : MiscReg { 48 FloatInexact = 0x1, 49 FloatUnderflow = 0x2, 50 FloatOverflow = 0x4, 51 FloatDivZero = 0x8, 52 FloatInvalid = 0x10 53}; 54
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| 55/* 56 * In RISC-V, exception and interrupt codes share some values. They can be 57 * differentiated by an 'Interrupt' flag that is enabled for interrupt faults 58 * but not exceptions. The full fault cause can be computed by placing the 59 * exception (or interrupt) code in the least significant bits of the CAUSE 60 * CSR and then setting the highest bit of CAUSE with the 'Interrupt' flag. 61 * For more details on exception causes, see Chapter 3.1.20 of the RISC-V 62 * privileged specification v 1.10. Codes are enumerated in Table 3.6. 63 */
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56enum ExceptionCode : MiscReg { 57 INST_ADDR_MISALIGNED = 0, 58 INST_ACCESS = 1, 59 INST_ILLEGAL = 2, 60 BREAKPOINT = 3, 61 LOAD_ADDR_MISALIGNED = 4, 62 LOAD_ACCESS = 5, 63 STORE_ADDR_MISALIGNED = 6, 64 AMO_ADDR_MISALIGNED = 6, 65 STORE_ACCESS = 7, 66 AMO_ACCESS = 7, 67 ECALL_USER = 8, 68 ECALL_SUPER = 9, 69 ECALL_MACHINE = 11, 70 INST_PAGE = 12, 71 LOAD_PAGE = 13, 72 STORE_PAGE = 15,
| 64enum ExceptionCode : MiscReg { 65 INST_ADDR_MISALIGNED = 0, 66 INST_ACCESS = 1, 67 INST_ILLEGAL = 2, 68 BREAKPOINT = 3, 69 LOAD_ADDR_MISALIGNED = 4, 70 LOAD_ACCESS = 5, 71 STORE_ADDR_MISALIGNED = 6, 72 AMO_ADDR_MISALIGNED = 6, 73 STORE_ACCESS = 7, 74 AMO_ACCESS = 7, 75 ECALL_USER = 8, 76 ECALL_SUPER = 9, 77 ECALL_MACHINE = 11, 78 INST_PAGE = 12, 79 LOAD_PAGE = 13, 80 STORE_PAGE = 15,
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73 AMO_PAGE = 15
| 81 AMO_PAGE = 15, 82 83 INT_SOFTWARE_USER = 0, 84 INT_SOFTWARE_SUPER = 1, 85 INT_SOFTWARE_MACHINE = 3, 86 INT_TIMER_USER = 4, 87 INT_TIMER_SUPER = 5, 88 INT_TIMER_MACHINE = 7, 89 INT_EXT_USER = 8, 90 INT_EXT_SUPER = 9, 91 INT_EXT_MACHINE = 11, 92 NumInterruptTypes
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74}; 75 76class RiscvFault : public FaultBase 77{ 78 protected: 79 const FaultName _name; 80 const bool _interrupt; 81 ExceptionCode _code; 82 83 RiscvFault(FaultName n, bool i, ExceptionCode c) 84 : _name(n), _interrupt(i), _code(c) 85 {} 86 87 FaultName name() const override { return _name; } 88 bool isInterrupt() const { return _interrupt; } 89 ExceptionCode exception() const { return _code; } 90 virtual MiscReg trap_value() const { return 0; } 91 92 virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst); 93 void invoke(ThreadContext *tc, const StaticInstPtr &inst) override; 94}; 95 96class Reset : public FaultBase 97{ 98 private: 99 const FaultName _name; 100 101 public: 102 Reset() : _name("reset") {} 103 FaultName name() const override { return _name; } 104 105 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 106 StaticInst::nullStaticInstPtr) override; 107}; 108
| 93}; 94 95class RiscvFault : public FaultBase 96{ 97 protected: 98 const FaultName _name; 99 const bool _interrupt; 100 ExceptionCode _code; 101 102 RiscvFault(FaultName n, bool i, ExceptionCode c) 103 : _name(n), _interrupt(i), _code(c) 104 {} 105 106 FaultName name() const override { return _name; } 107 bool isInterrupt() const { return _interrupt; } 108 ExceptionCode exception() const { return _code; } 109 virtual MiscReg trap_value() const { return 0; } 110 111 virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst); 112 void invoke(ThreadContext *tc, const StaticInstPtr &inst) override; 113}; 114 115class Reset : public FaultBase 116{ 117 private: 118 const FaultName _name; 119 120 public: 121 Reset() : _name("reset") {} 122 FaultName name() const override { return _name; } 123 124 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 125 StaticInst::nullStaticInstPtr) override; 126}; 127
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| 128class InterruptFault : public RiscvFault 129{ 130 public: 131 InterruptFault(ExceptionCode c) : RiscvFault("interrupt", true, c) {} 132 InterruptFault(int c) : InterruptFault(static_cast<ExceptionCode>(c)) {} 133}; 134
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109class InstFault : public RiscvFault 110{ 111 protected: 112 const ExtMachInst _inst; 113 114 public: 115 InstFault(FaultName n, const ExtMachInst inst) 116 : RiscvFault(n, false, INST_ILLEGAL), _inst(inst) 117 {} 118 119 MiscReg trap_value() const override { return _inst; } 120}; 121 122class UnknownInstFault : public InstFault 123{ 124 public: 125 UnknownInstFault(const ExtMachInst inst) 126 : InstFault("Unknown instruction", inst) 127 {} 128 129 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 130}; 131 132class IllegalInstFault : public InstFault 133{ 134 private: 135 const std::string reason; 136 137 public: 138 IllegalInstFault(std::string r, const ExtMachInst inst) 139 : InstFault("Illegal instruction", inst) 140 {} 141 142 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 143}; 144 145class UnimplementedFault : public InstFault 146{ 147 private: 148 const std::string instName; 149 150 public: 151 UnimplementedFault(std::string name, const ExtMachInst inst) 152 : InstFault("Unimplemented instruction", inst), 153 instName(name) 154 {} 155 156 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 157}; 158 159class IllegalFrmFault: public InstFault 160{ 161 private: 162 const uint8_t frm; 163 164 public: 165 IllegalFrmFault(uint8_t r, const ExtMachInst inst) 166 : InstFault("Illegal floating-point rounding mode", inst), 167 frm(r) 168 {} 169 170 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 171}; 172 173class AddressFault : public RiscvFault 174{ 175 private: 176 const Addr _addr; 177 178 public: 179 AddressFault(const Addr addr, ExceptionCode code) 180 : RiscvFault("Address", false, code), _addr(addr) 181 {} 182 183 MiscReg trap_value() const override { return _addr; } 184}; 185 186class BreakpointFault : public RiscvFault 187{ 188 private: 189 const PCState pcState; 190 191 public: 192 BreakpointFault(const PCState &pc) 193 : RiscvFault("Breakpoint", false, BREAKPOINT), pcState(pc) 194 {} 195 196 MiscReg trap_value() const override { return pcState.pc(); } 197 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 198}; 199 200class SyscallFault : public RiscvFault 201{ 202 public: 203 SyscallFault(PrivilegeMode prv) 204 : RiscvFault("System call", false, ECALL_USER) 205 { 206 switch (prv) { 207 case PRV_U: 208 _code = ECALL_USER; 209 break; 210 case PRV_S: 211 _code = ECALL_SUPER; 212 break; 213 case PRV_M: 214 _code = ECALL_MACHINE; 215 break; 216 default: 217 panic("Unknown privilege mode %d.", prv); 218 break; 219 } 220 } 221 222 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 223}; 224 225} // namespace RiscvISA 226 227#endif // __ARCH_RISCV_FAULTS_HH__
| 135class InstFault : public RiscvFault 136{ 137 protected: 138 const ExtMachInst _inst; 139 140 public: 141 InstFault(FaultName n, const ExtMachInst inst) 142 : RiscvFault(n, false, INST_ILLEGAL), _inst(inst) 143 {} 144 145 MiscReg trap_value() const override { return _inst; } 146}; 147 148class UnknownInstFault : public InstFault 149{ 150 public: 151 UnknownInstFault(const ExtMachInst inst) 152 : InstFault("Unknown instruction", inst) 153 {} 154 155 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 156}; 157 158class IllegalInstFault : public InstFault 159{ 160 private: 161 const std::string reason; 162 163 public: 164 IllegalInstFault(std::string r, const ExtMachInst inst) 165 : InstFault("Illegal instruction", inst) 166 {} 167 168 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 169}; 170 171class UnimplementedFault : public InstFault 172{ 173 private: 174 const std::string instName; 175 176 public: 177 UnimplementedFault(std::string name, const ExtMachInst inst) 178 : InstFault("Unimplemented instruction", inst), 179 instName(name) 180 {} 181 182 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 183}; 184 185class IllegalFrmFault: public InstFault 186{ 187 private: 188 const uint8_t frm; 189 190 public: 191 IllegalFrmFault(uint8_t r, const ExtMachInst inst) 192 : InstFault("Illegal floating-point rounding mode", inst), 193 frm(r) 194 {} 195 196 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 197}; 198 199class AddressFault : public RiscvFault 200{ 201 private: 202 const Addr _addr; 203 204 public: 205 AddressFault(const Addr addr, ExceptionCode code) 206 : RiscvFault("Address", false, code), _addr(addr) 207 {} 208 209 MiscReg trap_value() const override { return _addr; } 210}; 211 212class BreakpointFault : public RiscvFault 213{ 214 private: 215 const PCState pcState; 216 217 public: 218 BreakpointFault(const PCState &pc) 219 : RiscvFault("Breakpoint", false, BREAKPOINT), pcState(pc) 220 {} 221 222 MiscReg trap_value() const override { return pcState.pc(); } 223 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 224}; 225 226class SyscallFault : public RiscvFault 227{ 228 public: 229 SyscallFault(PrivilegeMode prv) 230 : RiscvFault("System call", false, ECALL_USER) 231 { 232 switch (prv) { 233 case PRV_U: 234 _code = ECALL_USER; 235 break; 236 case PRV_S: 237 _code = ECALL_SUPER; 238 break; 239 case PRV_M: 240 _code = ECALL_MACHINE; 241 break; 242 default: 243 panic("Unknown privilege mode %d.", prv); 244 break; 245 } 246 } 247 248 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 249}; 250 251} // namespace RiscvISA 252 253#endif // __ARCH_RISCV_FAULTS_HH__
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