1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Authors: Alec Roelke
31 * Robert Scheffel
32 */
33
34#ifndef __ARCH_RISCV_FAULTS_HH__
35#define __ARCH_RISCV_FAULTS_HH__
36
37#include <string>
38
39#include "arch/riscv/registers.hh"
40#include "cpu/thread_context.hh"
41#include "sim/faults.hh"
42
43namespace RiscvISA
44{
45
46enum FloatException : MiscReg {
47 FloatInexact = 0x1,
48 FloatUnderflow = 0x2,
49 FloatOverflow = 0x4,
50 FloatDivZero = 0x8,
51 FloatInvalid = 0x10
52};
53
54enum ExceptionCode : MiscReg {
55 INST_ADDR_MISALIGNED = 0,
56 INST_ACCESS = 1,
57 INST_ILLEGAL = 2,
58 BREAKPOINT = 3,
59 LOAD_ADDR_MISALIGNED = 4,
60 LOAD_ACCESS = 5,
61 STORE_ADDR_MISALIGNED = 6,
62 AMO_ADDR_MISALIGNED = 6,
63 STORE_ACCESS = 7,
64 AMO_ACCESS = 7,
65 ECALL_USER = 8,
66 ECALL_SUPER = 9,
67 ECALL_MACHINE = 11,
68 INST_PAGE = 12,
69 LOAD_PAGE = 13,
70 STORE_PAGE = 15,
71 AMO_PAGE = 15
72};
73
74/**
75 * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
76 * v1.10, accessible at www.riscv.org. in Figure 3.7. The main register that
77 * uses these fields is the MSTATUS register, which is shadowed by two others
78 * accessible at lower privilege levels (SSTATUS and USTATUS) that can't see
79 * the fields for higher privileges.
80 */
81BitUnion64(STATUS)
82 Bitfield<63> sd;
83 Bitfield<35, 34> sxl;
84 Bitfield<33, 32> uxl;
85 Bitfield<22> tsr;
86 Bitfield<21> tw;
87 Bitfield<20> tvm;
88 Bitfield<19> mxr;
89 Bitfield<18> sum;
90 Bitfield<17> mprv;
91 Bitfield<16, 15> xs;
92 Bitfield<14, 13> fs;
93 Bitfield<12, 11> mpp;
94 Bitfield<8> spp;
95 Bitfield<7> mpie;
96 Bitfield<5> spie;
97 Bitfield<4> upie;
98 Bitfield<3> mie;
99 Bitfield<1> sie;
100 Bitfield<0> uie;
101EndBitUnion(STATUS)
102
103/**
104 * These fields are specified in the RISC-V Instruction Set Manual, Volume II,
105 * v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. Both the MIP
106 * and MIE registers have the same fields, so accesses to either should use
107 * this bit union.
108 */
109BitUnion64(INTERRUPT)
110 Bitfield<11> mei;
111 Bitfield<9> sei;
112 Bitfield<8> uei;
113 Bitfield<7> mti;
114 Bitfield<5> sti;
115 Bitfield<4> uti;
116 Bitfield<3> msi;
117 Bitfield<1> ssi;
118 Bitfield<0> usi;
119EndBitUnion(INTERRUPT)
120
121class RiscvFault : public FaultBase
122{
123 protected:
124 const FaultName _name;
125 bool _interrupt;
126 const ExceptionCode _code;
127
128 RiscvFault(FaultName n, bool i, ExceptionCode c)
129 : _name(n), _interrupt(i), _code(c)
130 {}
131
132 FaultName name() const override { return _name; }
133 bool isInterrupt() const { return _interrupt; }
134 ExceptionCode exception() const { return _code; }
135 virtual MiscReg trap_value() const { return 0; }
136
137 virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst);
138 void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
139};
140
141class Reset : public FaultBase
142{
143
144 public:
145 Reset()
146 : _name("reset")
147 {}
148
149 FaultName
150 name() const override
151 {
152 return _name;
153 }
154
155 void
156 invoke(ThreadContext *tc, const StaticInstPtr &inst =
157 StaticInst::nullStaticInstPtr) override;
158
159 private:
160 const FaultName _name;
161};
162
163class InstFault : public RiscvFault
164{
165 protected:
166 const ExtMachInst _inst;
167
168 public:
169 InstFault(FaultName n, const ExtMachInst inst)
170 : RiscvFault(n, false, INST_ILLEGAL), _inst(inst)
171 {}
172
173 MiscReg trap_value() const override { return _inst; }
174};
175
176class UnknownInstFault : public InstFault
177{
178 public:
179 UnknownInstFault(const ExtMachInst inst)
180 : InstFault("Unknown instruction", inst)
181 {}
182
183 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
184};
185
186class IllegalInstFault : public InstFault
187{
188 private:
189 const std::string reason;
190
191 public:
192 IllegalInstFault(std::string r, const ExtMachInst inst)
193 : InstFault("Illegal instruction", inst)
194 {}
195
196 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
197};
198
199class UnimplementedFault : public InstFault
200{
201 private:
202 const std::string instName;
203
204 public:
205 UnimplementedFault(std::string name, const ExtMachInst inst)
206 : InstFault("Unimplemented instruction", inst),
207 instName(name)
208 {}
209
210 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
211};
212
213class IllegalFrmFault: public InstFault
214{
215 private:
216 const uint8_t frm;
217
218 public:
219 IllegalFrmFault(uint8_t r, const ExtMachInst inst)
220 : InstFault("Illegal floating-point rounding mode", inst),
221 frm(r)
222 {}
223
224 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
225};
226
227class AddressFault : public RiscvFault
228{
229 private:
230 const Addr _addr;
231
232 public:
233 AddressFault(const Addr addr, ExceptionCode code)
234 : RiscvFault("Address", false, code), _addr(addr)
235 {}
236
237 MiscReg trap_value() const override { return _addr; }
238};
239
240class BreakpointFault : public RiscvFault
241{
242 private:
243 const PCState pcState;
244
245 public:
246 BreakpointFault(const PCState &pc)
247 : RiscvFault("Breakpoint", false, BREAKPOINT), pcState(pc)
248 {}
249
250 MiscReg trap_value() const override { return pcState.pc(); }
251 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
252};
253
254class SyscallFault : public RiscvFault
255{
256 public:
257 // TODO: replace ECALL_USER with the appropriate privilege level of the
258 // caller
259 SyscallFault() : RiscvFault("System call", false, ECALL_USER) {}
260 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
261};
262
263} // namespace RiscvISA
264
265#endif // __ARCH_RISCV_FAULTS_HH__