1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Authors: Alec Roelke
31 * Robert Scheffel
32 */
33
34#ifndef __ARCH_RISCV_FAULTS_HH__
35#define __ARCH_RISCV_FAULTS_HH__
36
37#include <string>
38
39#include "cpu/thread_context.hh"
40#include "sim/faults.hh"
41
42namespace RiscvISA
43{
44
45const uint32_t FloatInexact = 1 << 0;
46const uint32_t FloatUnderflow = 1 << 1;
47const uint32_t FloatOverflow = 1 << 2;
48const uint32_t FloatDivZero = 1 << 3;
49const uint32_t FloatInvalid = 1 << 4;
50
51enum ExceptionCode {
52 INST_ADDR_MISALIGNED = 0,
53 INST_ACCESS = 1,
54 INST_ILLEGAL = 2,
55 BREAKPOINT = 3,
56 LOAD_ADDR_MISALIGNED = 4,
57 LOAD_ACCESS = 5,
58 STORE_ADDR_MISALIGNED = 6,
59 AMO_ADDR_MISALIGNED = 6,
60 STORE_ACCESS = 7,
61 AMO_ACCESS = 7,
62 ECALL_USER = 8,
63 ECALL_SUPER = 9,
64 ECALL_HYPER = 10,
65 ECALL_MACH = 11
66};
67
68enum InterruptCode {
69 SOFTWARE,
70 TIMER
71};
72
73class RiscvFault : public FaultBase
74{
75 protected:
76 const FaultName _name;
77 const ExceptionCode _code;
78 const InterruptCode _int;
79
80 RiscvFault(FaultName n, ExceptionCode c, InterruptCode i)
81 : _name(n), _code(c), _int(i)
82 {}
83
84 FaultName
85 name() const
86 {
87 return _name;
88 }
89
90 ExceptionCode
91 exception() const
92 {
93 return _code;
94 }
95
96 InterruptCode
97 interrupt() const
98 {
99 return _int;
100 }
101
102 virtual void
103 invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
104
105 void
106 invoke(ThreadContext *tc, const StaticInstPtr &inst);
107};
108
109class Reset : public FaultBase
110{
111
112 public:
113 Reset()
114 : _name("reset")
115 {}
116
117 FaultName
118 name() const override
119 {
120 return _name;
121 }
122
123 void
124 invoke(ThreadContext *tc, const StaticInstPtr &inst =
125 StaticInst::nullStaticInstPtr) override;
126
127 private:
128 const FaultName _name;
129};
130
131class UnknownInstFault : public RiscvFault
132{
133 public:
134 UnknownInstFault() : RiscvFault("Unknown instruction", INST_ILLEGAL,
135 SOFTWARE)
136 {}
137
138 void
139 invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
140};
141
142class IllegalInstFault : public RiscvFault
143{
144 private:
145 const std::string reason;
146 public:
147 IllegalInstFault(std::string r)
148 : RiscvFault("Illegal instruction", INST_ILLEGAL, SOFTWARE),
149 reason(r)
150 {}
151
152 void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
153};
154
155class UnimplementedFault : public RiscvFault
156{
157 private:
158 const std::string instName;
159 public:
160 UnimplementedFault(std::string name)
161 : RiscvFault("Unimplemented instruction", INST_ILLEGAL, SOFTWARE),
162 instName(name)
163 {}
164
165 void
166 invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
167};
168
169class IllegalFrmFault: public RiscvFault
170{
171 private:
172 const uint8_t frm;
173 public:
174 IllegalFrmFault(uint8_t r)
175 : RiscvFault("Illegal floating-point rounding mode", INST_ILLEGAL,
176 SOFTWARE),
177 frm(r)
178 {}
179
180 void invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
181};
182
183class BreakpointFault : public RiscvFault
184{
185 public:
186 BreakpointFault() : RiscvFault("Breakpoint", BREAKPOINT, SOFTWARE)
187 {}
188
189 void
190 invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
191};
192
193class SyscallFault : public RiscvFault
194{
195 public:
196 // TODO: replace ECALL_USER with the appropriate privilege level of the
197 // caller
198 SyscallFault() : RiscvFault("System call", ECALL_USER, SOFTWARE)
199 {}
200
201 void
202 invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
203};
204
205} // namespace RiscvISA
206
207#endif // __ARCH_RISCV_FAULTS_HH__