1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

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29 *
30 * Authors: Alec Roelke
31 * Robert Scheffel
32 */
33
34#ifndef __ARCH_RISCV_FAULTS_HH__
35#define __ARCH_RISCV_FAULTS_HH__
36
37#include <map>
38#include <string>
39
40#include "arch/riscv/isa.hh"
41#include "arch/riscv/registers.hh"
42#include "cpu/thread_context.hh"
43#include "sim/faults.hh"
44
45namespace RiscvISA
46{
47
48enum FloatException : MiscReg {
49 FloatInexact = 0x1,
50 FloatUnderflow = 0x2,
51 FloatOverflow = 0x4,
52 FloatDivZero = 0x8,
53 FloatInvalid = 0x10
54};
55
56enum ExceptionCode : MiscReg {
57 INST_ADDR_MISALIGNED = 0,
58 INST_ACCESS = 1,
59 INST_ILLEGAL = 2,
60 BREAKPOINT = 3,
61 LOAD_ADDR_MISALIGNED = 4,
62 LOAD_ACCESS = 5,
63 STORE_ADDR_MISALIGNED = 6,
64 AMO_ADDR_MISALIGNED = 6,
65 STORE_ACCESS = 7,
66 AMO_ACCESS = 7,
67 ECALL_USER = 8,
68 ECALL_SUPER = 9,
69 ECALL_MACHINE = 11,
70 INST_PAGE = 12,
71 LOAD_PAGE = 13,
72 STORE_PAGE = 15,
73 AMO_PAGE = 15
74};
75
76class RiscvFault : public FaultBase
77{
78 protected:
79 const FaultName _name;
80 const bool _interrupt;
81 ExceptionCode _code;

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101 public:
102 Reset() : _name("reset") {}
103 FaultName name() const override { return _name; }
104
105 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
106 StaticInst::nullStaticInstPtr) override;
107};
108
109class InstFault : public RiscvFault
110{
111 protected:
112 const ExtMachInst _inst;
113
114 public:
115 InstFault(FaultName n, const ExtMachInst inst)
116 : RiscvFault(n, false, INST_ILLEGAL), _inst(inst)

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