1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the

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22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Alec Roelke
30 */
31
32#ifndef __ARCH_RISCV_FAULTS_HH__
33#define __ARCH_RISCV_FAULTS_HH__
34
35#include <string>
36
37#include "cpu/thread_context.hh"

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99
100 virtual void
101 invoke_se(ThreadContext *tc, const StaticInstPtr &inst);
102
103 void
104 invoke(ThreadContext *tc, const StaticInstPtr &inst);
105};
106
107
108class UnknownInstFault : public RiscvFault
109{
110 public:
111 UnknownInstFault() : RiscvFault("Unknown instruction", INST_ILLEGAL,
112 SOFTWARE)
113 {}
114
115 void

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