1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

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90 virtual MiscReg trap_value() const { return 0; }
91
92 virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst);
93 void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
94};
95
96class Reset : public FaultBase
97{
98 private:
99 const FaultName _name;
100
101 public:
102 Reset() : _name("reset") {}
103 FaultName name() const override { return _name; }
104
105 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
106 StaticInst::nullStaticInstPtr) override;
107};
108
109class InstFault : public RiscvFault
110{
111 protected:
112 const ExtMachInst _inst;
113
114 public:

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