faults.cc (13548:b76f99d052bb) faults.cc (13612:12ae022f3a30)
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

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115 break;
116 default:
117 panic("Unknown privilege mode %d.", prv);
118 break;
119 }
120
121 // Set fault cause, privilege, and return PC
122 tc->setMiscReg(cause,
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

--- 106 unchanged lines hidden (view full) ---

115 break;
116 default:
117 panic("Unknown privilege mode %d.", prv);
118 break;
119 }
120
121 // Set fault cause, privilege, and return PC
122 tc->setMiscReg(cause,
123 (isInterrupt() << (sizeof(MiscReg) * 4 - 1)) | _code);
123 (isInterrupt() << (sizeof(uint64_t) * 4 - 1)) | _code);
124 tc->setMiscReg(epc, tc->instAddr());
125 tc->setMiscReg(tval, trap_value());
126 tc->setMiscReg(MISCREG_PRV, prv);
127 tc->setMiscReg(MISCREG_STATUS, status);
128
129 // Set PC to fault handler address
130 Addr addr = tc->readMiscReg(tvec) >> 2;
131 if (isInterrupt() && bits(tc->readMiscReg(tvec), 1, 0) == 1)

--- 66 unchanged lines hidden --- 		124 tc->setMiscReg(epc, tc->instAddr());
125 tc->setMiscReg(tval, trap_value());
126 tc->setMiscReg(MISCREG_PRV, prv);
127 tc->setMiscReg(MISCREG_STATUS, status);
128
129 // Set PC to fault handler address
130 Addr addr = tc->readMiscReg(tvec) >> 2;
131 if (isInterrupt() && bits(tc->readMiscReg(tvec), 1, 0) == 1)

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