faults.cc (13547:2aff46b9bbc5) faults.cc (13548:b76f99d052bb)
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

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56 PCState pcState = tc->pcState();
57
58 if (FullSystem) {
59 PrivilegeMode pp = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV);
60 PrivilegeMode prv = PRV_M;
61 STATUS status = tc->readMiscReg(MISCREG_STATUS);
62
63 // Set fault handler privilege mode
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

--- 47 unchanged lines hidden (view full) ---

56 PCState pcState = tc->pcState();
57
58 if (FullSystem) {
59 PrivilegeMode pp = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV);
60 PrivilegeMode prv = PRV_M;
61 STATUS status = tc->readMiscReg(MISCREG_STATUS);
62
63 // Set fault handler privilege mode
64 if (pp != PRV_M &&
65 bits(tc->readMiscReg(MISCREG_MEDELEG), _code) != 0) {
66 prv = PRV_S;
64 if (isInterrupt()) {
65 if (pp != PRV_M &&
66 bits(tc->readMiscReg(MISCREG_MIDELEG), _code) != 0) {
67 prv = PRV_S;
68 }
69 if (pp == PRV_U &&
70 bits(tc->readMiscReg(MISCREG_SIDELEG), _code) != 0) {
71 prv = PRV_U;
72 }
73 } else {
74 if (pp != PRV_M &&
75 bits(tc->readMiscReg(MISCREG_MEDELEG), _code) != 0) {
76 prv = PRV_S;
77 }
78 if (pp == PRV_U &&
79 bits(tc->readMiscReg(MISCREG_SEDELEG), _code) != 0) {
80 prv = PRV_U;
81 }
67 }
82 }
68 if (pp == PRV_U &&
69 bits(tc->readMiscReg(MISCREG_SEDELEG), _code) != 0) {
70 prv = PRV_U;
71 }
72
73 // Set fault registers and status
74 MiscRegIndex cause, epc, tvec, tval;
75 switch (prv) {
76 case PRV_U:
77 cause = MISCREG_UCAUSE;
78 epc = MISCREG_UEPC;
79 tvec = MISCREG_UTVEC;

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111 tc->setMiscReg(cause,
112 (isInterrupt() << (sizeof(MiscReg) * 4 - 1)) | _code);
113 tc->setMiscReg(epc, tc->instAddr());
114 tc->setMiscReg(tval, trap_value());
115 tc->setMiscReg(MISCREG_PRV, prv);
116 tc->setMiscReg(MISCREG_STATUS, status);
117
118 // Set PC to fault handler address
83
84 // Set fault registers and status
85 MiscRegIndex cause, epc, tvec, tval;
86 switch (prv) {
87 case PRV_U:
88 cause = MISCREG_UCAUSE;
89 epc = MISCREG_UEPC;
90 tvec = MISCREG_UTVEC;

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122 tc->setMiscReg(cause,
123 (isInterrupt() << (sizeof(MiscReg) * 4 - 1)) | _code);
124 tc->setMiscReg(epc, tc->instAddr());
125 tc->setMiscReg(tval, trap_value());
126 tc->setMiscReg(MISCREG_PRV, prv);
127 tc->setMiscReg(MISCREG_STATUS, status);
128
129 // Set PC to fault handler address
119 pcState.set(tc->readMiscReg(tvec) >> 2);
130 Addr addr = tc->readMiscReg(tvec) >> 2;
131 if (isInterrupt() && bits(tc->readMiscReg(tvec), 1, 0) == 1)
132 addr += 4 * _code;
133 pcState.set(addr);
120 } else {
121 invokeSE(tc, inst);
122 advancePC(pcState, inst);
123 }
124 tc->pcState(pcState);
125}
126
127void Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
128{
134 } else {
135 invokeSE(tc, inst);
136 advancePC(pcState, inst);
137 }
138 tc->pcState(pcState);
139}
140
141void Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
142{
129 if (FullSystem) {
130 tc->getCpuPtr()->clearInterrupts(tc->threadId());
131 tc->clearArchRegs();
132 }
133
134 tc->setMiscReg(MISCREG_PRV, PRV_M);
135 STATUS status = tc->readMiscReg(MISCREG_STATUS);
136 status.mie = 0;
137 status.mprv = 0;
138 tc->setMiscReg(MISCREG_STATUS, status);
139 tc->setMiscReg(MISCREG_MCAUSE, 0);
140
141 // Advance the PC to the implementation-defined reset vector

--- 47 unchanged lines hidden --- 		143 tc->setMiscReg(MISCREG_PRV, PRV_M);
144 STATUS status = tc->readMiscReg(MISCREG_STATUS);
145 status.mie = 0;
146 status.mprv = 0;
147 tc->setMiscReg(MISCREG_STATUS, status);
148 tc->setMiscReg(MISCREG_MCAUSE, 0);
149
150 // Advance the PC to the implementation-defined reset vector

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