faults.cc (12849:7f43ad13ebf0) faults.cc (13547:2aff46b9bbc5)
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

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126
127void Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
128{
129 if (FullSystem) {
130 tc->getCpuPtr()->clearInterrupts(tc->threadId());
131 tc->clearArchRegs();
132 }
133
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

--- 117 unchanged lines hidden (view full) ---

126
127void Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
128{
129 if (FullSystem) {
130 tc->getCpuPtr()->clearInterrupts(tc->threadId());
131 tc->clearArchRegs();
132 }
133
134 tc->setMiscReg(MISCREG_PRV, PRV_M);
135 STATUS status = tc->readMiscReg(MISCREG_STATUS);
136 status.mie = 0;
137 status.mprv = 0;
138 tc->setMiscReg(MISCREG_STATUS, status);
139 tc->setMiscReg(MISCREG_MCAUSE, 0);
140
134 // Advance the PC to the implementation-defined reset vector
135 PCState pc = static_cast<RiscvSystem *>(tc->getSystemPtr())->resetVect();
136 tc->pcState(pc);
137}
138
139void
140UnknownInstFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst)
141{

--- 40 unchanged lines hidden --- 		141 // Advance the PC to the implementation-defined reset vector
142 PCState pc = static_cast<RiscvSystem *>(tc->getSystemPtr())->resetVect();
143 tc->pcState(pc);
144}
145
146void
147UnknownInstFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst)
148{

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