faults.cc (12848:67652b15de3b) faults.cc (12849:7f43ad13ebf0)
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

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66 prv = PRV_S;
67 }
68 if (pp == PRV_U &&
69 bits(tc->readMiscReg(MISCREG_SEDELEG), _code) != 0) {
70 prv = PRV_U;
71 }
72
73 // Set fault registers and status
1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * Copyright (c) 2018 TU Dresden
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

--- 57 unchanged lines hidden (view full) ---

66 prv = PRV_S;
67 }
68 if (pp == PRV_U &&
69 bits(tc->readMiscReg(MISCREG_SEDELEG), _code) != 0) {
70 prv = PRV_U;
71 }
72
73 // Set fault registers and status
74 MiscRegIndex cause, epc, tvec;
74 MiscRegIndex cause, epc, tvec, tval;
75 switch (prv) {
76 case PRV_U:
77 cause = MISCREG_UCAUSE;
78 epc = MISCREG_UEPC;
79 tvec = MISCREG_UTVEC;
75 switch (prv) {
76 case PRV_U:
77 cause = MISCREG_UCAUSE;
78 epc = MISCREG_UEPC;
79 tvec = MISCREG_UTVEC;
80 tval = MISCREG_UTVAL;
80
81 status.upie = status.uie;
82 status.uie = 0;
83 break;
84 case PRV_S:
85 cause = MISCREG_SCAUSE;
86 epc = MISCREG_SEPC;
87 tvec = MISCREG_STVEC;
81
82 status.upie = status.uie;
83 status.uie = 0;
84 break;
85 case PRV_S:
86 cause = MISCREG_SCAUSE;
87 epc = MISCREG_SEPC;
88 tvec = MISCREG_STVEC;
89 tval = MISCREG_STVAL;
88
89 status.spp = pp;
90 status.spie = status.sie;
91 status.sie = 0;
92 break;
93 case PRV_M:
94 cause = MISCREG_MCAUSE;
95 epc = MISCREG_MEPC;
96 tvec = MISCREG_MTVEC;
90
91 status.spp = pp;
92 status.spie = status.sie;
93 status.sie = 0;
94 break;
95 case PRV_M:
96 cause = MISCREG_MCAUSE;
97 epc = MISCREG_MEPC;
98 tvec = MISCREG_MTVEC;
99 tval = MISCREG_MTVAL;
97
98 status.mpp = pp;
99 status.mpie = status.sie;
100 status.mie = 0;
101 break;
102 default:
103 panic("Unknown privilege mode %d.", prv);
104 break;
105 }
106
107 // Set fault cause, privilege, and return PC
108 tc->setMiscReg(cause,
109 (isInterrupt() << (sizeof(MiscReg) * 4 - 1)) | _code);
110 tc->setMiscReg(epc, tc->instAddr());
100
101 status.mpp = pp;
102 status.mpie = status.sie;
103 status.mie = 0;
104 break;
105 default:
106 panic("Unknown privilege mode %d.", prv);
107 break;
108 }
109
110 // Set fault cause, privilege, and return PC
111 tc->setMiscReg(cause,
112 (isInterrupt() << (sizeof(MiscReg) * 4 - 1)) | _code);
113 tc->setMiscReg(epc, tc->instAddr());
114 tc->setMiscReg(tval, trap_value());
111 tc->setMiscReg(MISCREG_PRV, prv);
112 tc->setMiscReg(MISCREG_STATUS, status);
113
114 // Set PC to fault handler address
115 pcState.set(tc->readMiscReg(tvec) >> 2);
116 } else {
117 invokeSE(tc, inst);
118 advancePC(pcState, inst);

--- 59 unchanged lines hidden --- 		115 tc->setMiscReg(MISCREG_PRV, prv);
116 tc->setMiscReg(MISCREG_STATUS, status);
117
118 // Set PC to fault handler address
119 pcState.set(tc->readMiscReg(tvec) >> 2);
120 } else {
121 invokeSE(tc, inst);
122 advancePC(pcState, inst);

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