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> #include "arch/riscv/isa.hh"
> #include "arch/riscv/registers.hh"
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< using namespace RiscvISA;
---
> namespace RiscvISA
> {
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< RiscvFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
---
> RiscvFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst)
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> PCState pcState = tc->pcState();
>
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< panic("Full system mode not supported for RISC-V.");
---
> PrivilegeMode pp = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV);
> PrivilegeMode prv = PRV_M;
> STATUS status = tc->readMiscReg(MISCREG_STATUS);
>
> // Set fault handler privilege mode
> if (pp != PRV_M &&
> bits(tc->readMiscReg(MISCREG_MEDELEG), _code) != 0) {
> prv = PRV_S;
> }
> if (pp == PRV_U &&
> bits(tc->readMiscReg(MISCREG_SEDELEG), _code) != 0) {
> prv = PRV_U;
> }
>
> // Set fault registers and status
> MiscRegIndex cause, epc, tvec;
> switch (prv) {
> case PRV_U:
> cause = MISCREG_UCAUSE;
> epc = MISCREG_UEPC;
> tvec = MISCREG_UTVEC;
>
> status.upie = status.uie;
> status.uie = 0;
> break;
> case PRV_S:
> cause = MISCREG_SCAUSE;
> epc = MISCREG_SEPC;
> tvec = MISCREG_STVEC;
>
> status.spp = pp;
> status.spie = status.sie;
> status.sie = 0;
> break;
> case PRV_M:
> cause = MISCREG_MCAUSE;
> epc = MISCREG_MEPC;
> tvec = MISCREG_MTVEC;
>
> status.mpp = pp;
> status.mpie = status.sie;
> status.mie = 0;
> break;
> default:
> panic("Unknown privilege mode %d.", prv);
> break;
> }
>
> // Set fault cause, privilege, and return PC
> tc->setMiscReg(cause,
> (isInterrupt() << (sizeof(MiscReg) * 4 - 1)) | _code);
> tc->setMiscReg(epc, tc->instAddr());
> tc->setMiscReg(MISCREG_PRV, prv);
> tc->setMiscReg(MISCREG_STATUS, status);
>
> // Set PC to fault handler address
> pcState.set(tc->readMiscReg(tvec) >> 2);
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< invoke_se(tc, inst);
< PCState pcState = tc->pcState();
---
> invokeSE(tc, inst);
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< tc->pcState(pcState);
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> tc->pcState(pcState);
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< UnknownInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
---
> UnknownInstFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst)
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< IllegalInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
---
> IllegalInstFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst)
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< UnimplementedFault::invoke_se(ThreadContext *tc,
---
> UnimplementedFault::invokeSE(ThreadContext *tc,
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< IllegalFrmFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
---
> IllegalFrmFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst)
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< BreakpointFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
---
> BreakpointFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst)
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< SyscallFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
---
> SyscallFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst)
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>
> } // namespace RiscvISA