1/*
2 * Copyright (c) 2016 RISC-V Foundation
3 * Copyright (c) 2016 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the

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22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Alec Roelke
30 */
31#include "arch/riscv/faults.hh"
32
33#include "arch/riscv/utility.hh"
34#include "cpu/thread_context.hh"
35#include "sim/debug.hh"
36#include "sim/full_system.hh"
37
38using namespace RiscvISA;
39
40void
41RiscvFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)

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51 } else {
52 invoke_se(tc, inst);
53 PCState pcState = tc->pcState();
54 advancePC(pcState, inst);
55 tc->pcState(pcState);
56 }
57}
58
59void
60UnknownInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
61{
62 panic("Unknown instruction 0x%08x at pc 0x%016llx", inst->machInst,
63 tc->pcState().pc());
64}
65
66void

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