1/* 2 * Copyright (c) 2012 Google |
3 * Copyright (c) 2017 The University of Virginia |
4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the --- 10 unchanged lines hidden (view full) --- 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Gabe Black |
30 * Alec Roelke |
31 */ 32 33#ifndef __ARCH_RISCV_DECODER_HH__ 34#define __ARCH_RISCV_DECODER_HH__ 35 36#include "arch/generic/decode_cache.hh" |
37#include "arch/riscv/isa_traits.hh" |
38#include "arch/riscv/types.hh" 39#include "base/misc.hh" 40#include "base/types.hh" 41#include "cpu/static_inst.hh" |
42#include "debug/Decode.hh" |
43 44namespace RiscvISA 45{ 46 47class ISA; 48class Decoder 49{ |
50 private: 51 DecodeCache::InstMap instMap; 52 bool mid; 53 |
54 protected: 55 //The extended machine instruction being generated 56 ExtMachInst emi; 57 bool instDone; 58 59 public: |
60 Decoder(ISA* isa=nullptr) 61 : mid(false), emi(NoopMachInst), instDone(false) |
62 {} 63 |
64 void process() {} 65 void reset() { instDone = false; } |
66 |
67 //Use this to give data to the decoder. This should be used 68 //when there is control flow. |
69 void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst); |
70 |
71 bool needMoreBytes() { return true; } 72 bool instReady() { return instDone; } |
73 void takeOverFrom(Decoder *old) {} 74 |
75 StaticInstPtr decodeInst(ExtMachInst mach_inst); 76 77 /// Decode a machine instruction. 78 /// @param mach_inst The binary instruction to decode. 79 /// @retval A pointer to the corresponding StaticInst object. |
80 StaticInstPtr decode(ExtMachInst mach_inst, Addr addr); |
81 |
82 StaticInstPtr decode(RiscvISA::PCState &nextPC); |
83}; 84 85} // namespace RiscvISA 86 87#endif // __ARCH_RISCV_DECODER_HH__ |