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> * Copyright (c) 2017 The University of Virginia
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> * Alec Roelke
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> #include "arch/riscv/isa_traits.hh"
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> #include "debug/Decode.hh"
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> private:
> DecodeCache::InstMap instMap;
> bool mid;
>
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< Decoder(ISA* isa = nullptr) : instDone(false)
---
> Decoder(ISA* isa=nullptr)
> : mid(false), emi(NoopMachInst), instDone(false)
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< void
< process()
< {
< }
---
> void process() {}
> void reset() { instDone = false; }
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< void
< reset()
< {
< instDone = false;
< }
<
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< void
< moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
< {
< emi = inst;
< instDone = true;
< }
---
> void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
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< bool
< needMoreBytes()
< {
< return true;
< }
<
< bool
< instReady()
< {
< return instDone;
< }
<
---
> bool needMoreBytes() { return true; }
> bool instReady() { return instDone; }
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< protected:
< /// A cache of decoded instruction objects.
< static GenericISA::BasicDecodeCache defaultCache;
<
< public:
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< StaticInstPtr
< decode(ExtMachInst mach_inst, Addr addr)
< {
< return defaultCache.decode(this, mach_inst, addr);
< }
---
> StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
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< StaticInstPtr
< decode(RiscvISA::PCState &nextPC)
< {
< if (!instDone)
< return nullptr;
< instDone = false;
< return decode(emi, nextPC.instAddr());
< }
---
> StaticInstPtr decode(RiscvISA::PCState &nextPC);