1/* 2 * Copyright (c) 2012 Google
| 1/* 2 * Copyright (c) 2012 Google
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| 3 * Copyright (c) 2017 The University of Virginia
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3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black
| 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Gabe Black
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| 30 * Alec Roelke
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29 */ 30 31#ifndef __ARCH_RISCV_DECODER_HH__ 32#define __ARCH_RISCV_DECODER_HH__ 33 34#include "arch/generic/decode_cache.hh"
| 31 */ 32 33#ifndef __ARCH_RISCV_DECODER_HH__ 34#define __ARCH_RISCV_DECODER_HH__ 35 36#include "arch/generic/decode_cache.hh"
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| 37#include "arch/riscv/isa_traits.hh"
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35#include "arch/riscv/types.hh" 36#include "base/misc.hh" 37#include "base/types.hh" 38#include "cpu/static_inst.hh"
| 38#include "arch/riscv/types.hh" 39#include "base/misc.hh" 40#include "base/types.hh" 41#include "cpu/static_inst.hh"
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| 42#include "debug/Decode.hh"
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39 40namespace RiscvISA 41{ 42 43class ISA; 44class Decoder 45{
| 43 44namespace RiscvISA 45{ 46 47class ISA; 48class Decoder 49{
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| 50 private: 51 DecodeCache::InstMap instMap; 52 bool mid; 53
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46 protected: 47 //The extended machine instruction being generated 48 ExtMachInst emi; 49 bool instDone; 50 51 public:
| 54 protected: 55 //The extended machine instruction being generated 56 ExtMachInst emi; 57 bool instDone; 58 59 public:
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52 Decoder(ISA* isa = nullptr) : instDone(false)
| 60 Decoder(ISA* isa=nullptr) 61 : mid(false), emi(NoopMachInst), instDone(false)
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53 {} 54
| 62 {} 63
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55 void 56 process() 57 { 58 }
| 64 void process() {} 65 void reset() { instDone = false; }
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59
| 66
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60 void 61 reset() 62 { 63 instDone = false; 64 } 65
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66 //Use this to give data to the decoder. This should be used 67 //when there is control flow.
| 67 //Use this to give data to the decoder. This should be used 68 //when there is control flow.
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68 void 69 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) 70 { 71 emi = inst; 72 instDone = true; 73 }
| 69 void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
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74
| 70
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75 bool 76 needMoreBytes() 77 { 78 return true; 79 } 80 81 bool 82 instReady() 83 { 84 return instDone; 85 } 86
| 71 bool needMoreBytes() { return true; } 72 bool instReady() { return instDone; }
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87 void takeOverFrom(Decoder *old) {} 88
| 73 void takeOverFrom(Decoder *old) {} 74
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89 protected: 90 /// A cache of decoded instruction objects. 91 static GenericISA::BasicDecodeCache defaultCache; 92 93 public:
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94 StaticInstPtr decodeInst(ExtMachInst mach_inst); 95 96 /// Decode a machine instruction. 97 /// @param mach_inst The binary instruction to decode. 98 /// @retval A pointer to the corresponding StaticInst object.
| 75 StaticInstPtr decodeInst(ExtMachInst mach_inst); 76 77 /// Decode a machine instruction. 78 /// @param mach_inst The binary instruction to decode. 79 /// @retval A pointer to the corresponding StaticInst object.
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99 StaticInstPtr 100 decode(ExtMachInst mach_inst, Addr addr) 101 { 102 return defaultCache.decode(this, mach_inst, addr); 103 }
| 80 StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
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104
| 81
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105 StaticInstPtr 106 decode(RiscvISA::PCState &nextPC) 107 { 108 if (!instDone) 109 return nullptr; 110 instDone = false; 111 return decode(emi, nextPC.instAddr()); 112 }
| 82 StaticInstPtr decode(RiscvISA::PCState &nextPC);
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113}; 114 115} // namespace RiscvISA 116 117#endif // __ARCH_RISCV_DECODER_HH__
| 83}; 84 85} // namespace RiscvISA 86 87#endif // __ARCH_RISCV_DECODER_HH__
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