1/*
2 * Copyright (c) 2012 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_RISCV_DECODER_HH__
32#define __ARCH_RISCV_DECODER_HH__
33
34#include "arch/generic/decode_cache.hh"
35#include "arch/riscv/types.hh"
36#include "base/misc.hh"
37#include "base/types.hh"
38#include "cpu/static_inst.hh"
39
40namespace RiscvISA
41{
42
43class ISA;
44class Decoder
45{
46 protected:
47 //The extended machine instruction being generated
48 ExtMachInst emi;
49 bool instDone;
50
51 public:
52 Decoder(ISA* isa = nullptr) : instDone(false)
53 {}
54
55 void
56 process()
57 {
58 }
59
60 void
61 reset()
62 {
63 instDone = false;
64 }
65
66 //Use this to give data to the decoder. This should be used
67 //when there is control flow.
68 void
69 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
70 {
71 emi = inst;
72 instDone = true;
73 }
74
75 bool
76 needMoreBytes()
77 {
78 return true;
79 }
80
81 bool
82 instReady()
83 {
84 return instDone;
85 }
86
87 void takeOverFrom(Decoder *old) {}
88
89 protected:
90 /// A cache of decoded instruction objects.
91 static GenericISA::BasicDecodeCache defaultCache;
92
93 public:
94 StaticInstPtr decodeInst(ExtMachInst mach_inst);
95
96 /// Decode a machine instruction.
97 /// @param mach_inst The binary instruction to decode.
98 /// @retval A pointer to the corresponding StaticInst object.
99 StaticInstPtr
100 decode(ExtMachInst mach_inst, Addr addr)
101 {
102 return defaultCache.decode(this, mach_inst, addr);
103 }
104
105 StaticInstPtr
106 decode(RiscvISA::PCState &nextPC)
107 {
108 if (!instDone)
109 return nullptr;
110 instDone = false;
111 return decode(emi, nextPC.instAddr());
112 }
113};
114
115} // namespace RiscvISA
116
117#endif // __ARCH_RISCV_DECODER_HH__