SConscript (12222:6db0fc7407a5) SConscript (12808:f275fd1244ce)
1# -*- mode:python -*-
2
3# Copyright (c) 2013 ARM Limited
4# Copyright (c) 2014 Sven Karlsson
5# All rights reserved
6#
7# The license below extends only to copyright in the software and shall
8# not be construed as granting a license to any other intellectual

--- 43 unchanged lines hidden (view full) ---

52 Source('interrupts.cc')
53 Source('locked_mem.cc')
54 Source('process.cc')
55 Source('pagetable.cc')
56 Source('remote_gdb.cc')
57 Source('stacktrace.cc')
58 Source('tlb.cc')
59 Source('system.cc')
1# -*- mode:python -*-
2
3# Copyright (c) 2013 ARM Limited
4# Copyright (c) 2014 Sven Karlsson
5# All rights reserved
6#
7# The license below extends only to copyright in the software and shall
8# not be construed as granting a license to any other intellectual

--- 43 unchanged lines hidden (view full) ---

52 Source('interrupts.cc')
53 Source('locked_mem.cc')
54 Source('process.cc')
55 Source('pagetable.cc')
56 Source('remote_gdb.cc')
57 Source('stacktrace.cc')
58 Source('tlb.cc')
59 Source('system.cc')
60 Source('utility.cc')
60
61 Source('linux/process.cc')
62 Source('linux/linux.cc')
63
61
62 Source('linux/process.cc')
63 Source('linux/linux.cc')
64
65 Source('bare_metal/system.cc')
66
64 SimObject('RiscvInterrupts.py')
65 SimObject('RiscvISA.py')
66 SimObject('RiscvTLB.py')
67 SimObject('RiscvSystem.py')
68
69 DebugFlag('RiscvMisc')
70 DebugFlag('RiscvTLB')
71
72 # Add in files generated by the ISA description.
73 ISADesc('isa/main.isa')
67 SimObject('RiscvInterrupts.py')
68 SimObject('RiscvISA.py')
69 SimObject('RiscvTLB.py')
70 SimObject('RiscvSystem.py')
71
72 DebugFlag('RiscvMisc')
73 DebugFlag('RiscvTLB')
74
75 # Add in files generated by the ISA description.
76 ISADesc('isa/main.isa')