utility.hh (7506:e76cc0ca16cc) utility.hh (7627:3b0c4b819651)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

--- 47 unchanged lines hidden (view full) ---

56
57/**
58 * Function to ensure ISA semantics about 0 registers.
59 * @param tc The thread context.
60 */
61template <class TC>
62void zeroRegisters(TC *tc);
63
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

--- 47 unchanged lines hidden (view full) ---

56
57/**
58 * Function to ensure ISA semantics about 0 registers.
59 * @param tc The thread context.
60 */
61template <class TC>
62void zeroRegisters(TC *tc);
63
64// Instruction address compression hooks
65static inline Addr
66realPCToFetchPC(const Addr &addr)
67{
68 return addr;
69}
70
71static inline Addr
72fetchPCToRealPC(const Addr &addr)
73{
74 return addr;
75}
76
77// the size of "fetched" instructions
78static inline size_t
79fetchInstSize()
80{
81 return sizeof(MachInst);
82}
83
84static inline MachInst
85makeRegisterCopy(int dest, int src)
86{
87 panic("makeRegisterCopy not implemented");
88 return 0;
89}
90
91inline void
92startupCPU(ThreadContext *tc, int cpuId)
93{
94 tc->activate(0);
95}
96
97template <class XC>
98Fault

--- 16 unchanged lines hidden --- 		64inline void
65startupCPU(ThreadContext *tc, int cpuId)
66{
67 tc->activate(0);
68}
69
70template <class XC>
71Fault

--- 16 unchanged lines hidden ---