tlb.hh (10905:a6ca6831e775) tlb.hh (11168:f98eb2da15a4)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without

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167 Translation *translation, Mode mode);
168 /** Stub function for CheckerCPU compilation support. Power ISA not
169 * supported by Checker at the moment
170 */
171 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
172 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
173
174 // Checkpointing
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without

--- 158 unchanged lines hidden (view full) ---

167 Translation *translation, Mode mode);
168 /** Stub function for CheckerCPU compilation support. Power ISA not
169 * supported by Checker at the moment
170 */
171 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
172 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
173
174 // Checkpointing
175 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
176 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
175 void serialize(CheckpointOut &cp) const override;
176 void unserialize(CheckpointIn &cp) override;
177
178 void regStats();
179};
180
181} // namespace PowerISA
182
183#endif // __ARCH_POWER_TLB_HH__
177
178 void regStats();
179};
180
181} // namespace PowerISA
182
183#endif // __ARCH_POWER_TLB_HH__